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HTG2190 Datasheet(PDF) 16 Page - Holtek Semiconductor Inc |
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HTG2190 Datasheet(HTML) 16 Page - Holtek Semiconductor Inc |
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16 / 50 page ![]() HTG2190 Rev. 1.20 16 July 5, 2002 SSL3 SSL2 SSL1 SSL0 Description x0 0 0 The Pad of common 0 is connected to common 0 signal and the Pad of common 1 is connected to common 1 signal and so on. x0 0 1 The Pad of common 0 is connected to common 1 signal and the Pad of common 1 is connected to common 2 signal and so on. x0 1 0 The Pad of common 0 is connected to common 2 signal and the Pad of common 1 is connected to common 3 signal and so on. x0 1 1 The Pad of common 0 is connected to common 3 signal and the Pad of common 1 is connected to common 4 signal and so on. x1 0 0 The Pad of common 0 is connected to common 4 signal and the Pad of common 1 is connected to common 5 signal and so on. x1 0 1 The Pad of common 0 is connected to common 5 signal and the Pad of common 1 is connected to common 6 signal and so on. x1 1 0 The Pad of common 0 is connected to common 6 signal and the Pad of common 1 is connected to common 7 signal and so on. x1 1 1 The Pad of common 0 is connected to common 7 signal and the Pad of common 1 is connected to common 0 signal and so on. COMR register Indirect addressing register Locations 00H and 02H are indirect addressing regis- ters that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H, while writing to it indirectly results in no operation. The data movement function between two indirect ad- dressing registers is not supported. The memory pointer registers MP0 and MP1, are 8-bit registers used to ac- cess the data memory by combining corresponding indi- rect addressing registers, Bank1~Bank11, Bank14 and Bank15 can use MP1 only. Accumulator The accumulator closely relates to ALU operations. It is also mapped to location 05H of the data memory and is the one which can operate with immediate data. The data movement between two data memory must pass through the accumulator. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions: · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data operation but can also change the status register. Status register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and Watchdog time-out flag (TO). It also records the status information and controls the oper- ation sequence. With the exception of the TO and PD flags, bits in the status register can be altered by instructions like any other register. Any data written into the status register will not change the TO or PD flags. In addition, opera- tions related to the status register may give different re- sults from those intended. The TO and PD flags can only be changed by a system power up, Watchdog Timer overflow, executing the HALT instruction and clearing the Watchdog Timer. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or exe- cuting the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status register are important and the subroutine can corrupt the status register, the programmer must take precautions to save it properly. Interrupt The HTG2190 provides external and a PWM D/A inter- rupt and internal timer/event counter interrupts. The in- terrupt control register (INTC;0BH, INTCH;1EH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. |
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