HTG2190 datasheet(17/50 Pages) HOLTEK

17 / 50 page

HTG2190

Rev. 1.20

July 5, 2002

Once an interrupt subroutine is serviced, all other inter-

rupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flag is recorded. If a certain in-

terrupt needs servicing within the service routine, the EMI

bit and the corresponding INTC bit may be set to allow in-

terrupt nesting. If the stack is full, the interrupt request will

not be acknowledged, even if the related interrupt is en-

abled, until the SP is decremented. If immediate service is

desired, the stack must be prevented from becoming full.

All these kinds of interrupt have the wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter and A15~A13 bits onto the

stack and then branching to subroutines at specified lo-

cation(s) in the program memory. Only the program

counter are pushed and A15~A13 bits onto the stack. If

the contents of the register and Status register

(STATUS) are altered by the interrupt service program

which corrupt the desired control sequence, the con-

tents must be saved first.

External interrupt is triggered by a high to low transition

of INT which sets the related interrupt request flag (EIF;

bit 4 of INTC0). When the interrupt is enabled, and the

stack is not full and the external interrupt is active, a sub-

routine call to location 04H will occur. The interrupt re-

quest flag (EIF) and EMI bits will be cleared to disable

other interrupts.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F; bit 5 of INTC0), caused by a

Timer/Event Counter 0 overflow. When the interrupt is

enabled, and the stack is not full and the T0F bit is set, a

subroutine call to location 08H will occur. The related in-

terrupt request flag (T0F) will be reset and the

bit

cleared to disable further interrupts.

The Timer/Event Counter 1 and timer 2/3 interrupt is op-

erated in the same manner as Timer/Event Counter 0.

The related interrupt control bits ET1I and T1F of

Timer/Event Counter 1 are bit 3 and bit 6 of INTC0 re-

spectively. While ET2I/ET3I and T2F/T3F are the re-

lated control bits and the related request flags of

TMR2/TMR3, which locate at bit0/bit1 and bit4/bit5 of

the INTC1 respectively.

During the execution of an interrupt subroutine, other inter-

rupt acknowledgments are held until the RETI instruction is

executed or the EMI bit and the related interrupt control bit

are set to 1 (of course, if the stack is not full). To return from

the interrupt subroutine, the RET or RETI instruction may

be invoked. RETI will set the EMI bit to enable an interrupt

service, but RET will not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests,

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

External interrupt

04H

Timer/Event Counter 0 overflow

08H

Timer/Event Counter 1 overflow

0CH

Timer 2 overflow

10H

Timer 3 overflow

14H

PWM D/A interrupt

18H

The Timer/Event Counter 0/1 and timer 2/3 interrupt re-

quest flag (T0F/T1F/T2F/T3F), external interrupt request

flag (EIF), PWM D/A interrupt request flag (PWMF) enable

timer/ event counter 0/1/2/3 bit (ET0I/ET1I/ET2I/ ET3I),

enable PWM D/A interrupt bit (PWMI), enable external in-

terrupt bit (EEI) and enable master interrupt bit (EMI) form

Labels

Bits

Function

C is set if the operation results in a carry during an addition operation or if a borrow does not take

place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate through

carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the high-

est-order bit, or vice versa; otherwise OV is cleared.

PD is cleared when either a system power-up or executing the CLR WDT instruction. PD is set by

executing the HALT instruction.

TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a

WDT time-out.

6,7

Unused bit, read as

²0²

STATUS register

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