HTG2190 datasheet(28/50 Pages) HOLTEK

28 / 50 page

HTG2190

Rev. 1.20

July 5, 2002

SOUT is latch data at H to L by fixed mode

SERC

SCLKX

SCLKS

16K

fSYS/4

fSYS/8

fSYS/16

fSYS/32

fSYS/64

512

fSYS/128

256

fSYS/256

128

fSYS/512

At initial reset, the slave mode (external clock mode) is

selected. Moreover, the synchronous clock, along with

the input/output of the 8 bits serial data, is controlled as

follows:

· At master mode, after output of 8 clock from the SCLK

terminal, clock output is automatically suspended and

SCLK terminal is fixed at high level.

· At slave mode, after input of 8 clocks to the terminal,

subsequent clock inputs are masked.

Serial data output

By setting the parallel data to serial data registers

SERDATA individually and writing

²0² to SERC.0, it syn-

chronizes with the synchronous clock and serial data is

output at the SOUT terminal.

S y s t e m C l o c k

P r e s c a l e r

P W M D a t a

B u f f e r ( 2 8 H )

7 - b i t C o u n t e r

D a t a B u s

O v e r f l o w

. 0

S t a r t b i t

2 7 H . 0

D i v .

P W M I

. 2

C K

P E

C K

S i g n b i t

. 1

P W M D A C 1 f o r B Z

P W M D A C 2 f o r B Z

V D D

27H.1=1 buzzer

S y s t e m c l o c k

P r e s c a l e r

P W M D a t a

B u f f e r ( 2 8 H )

7 B i t s C o u n t e r

D a t a B u s

O v e r f l o w

P W M D A C 1 f o r 3 2 W S P K

. 0

S t a r t b i t

2 7 H . 0

D i v .

P W M I

. 2

C K

P E

C K

V D D

. 1

P W M D A C 2 f o r 3 2 W S P K

27H.1=0 speaker

S C L K

S O U T

S I N

I n p u t T e r m i n a l

C L K

S O U T

S I N

P B 2

H T G 2 1 9 0

E x t e r n a l

S e r i a l D e v i c e

( a ) M a s t e r m o d e

S C L K

S O U T

S I N

P B 2

C L K

S O U T

S I N

I n p u t T e r m i n a l

H T G 2 1 9 0

E x t e r n a l

S e r i a l D e v i c e

( b ) S l a v e m o d e

HTG2190 Datasheet(PDF) 28 Page - Holtek Semiconductor Inc

HTG2190 Datasheet(HTML) 28 Page - Holtek Semiconductor Inc

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