HTG2190 datasheet(20/50 Pages) HOLTEK

20 / 50 page

HTG2190

Rev. 1.20

July 5, 2002

flag is set to

²1² before entering the HALT mode, the

wake-up function of the related interrupt will be disabled.

To minimize power consumption, all I/O pins should be

carefully managed before entering the HALT status.

Reset

There are 3 ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a

²warm re -

set

² that resets only the PC and SP, leaving the other

circuits in their original state. Some registers remain un-

changed during any other reset conditions. Most regis-

ters are reset to their

²initial condition² when the reset

conditions are met. By examining the PD flag and TO

flag, the program can distinguish between different

²chip resets².

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² stands for ²unchange²

To guarantee that the system oscillator has started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses after a system

power up or when awakening from a HALT state.

When a system power up occurs, the SST delay is

added during the reset period. But when the reset co-

mes from the RES pin, the SST delay is disabled. Any

wake-up from HALT will enable the SST delay.

The functional unit chip reset status is shown in the ta-

ble.

Program Counter

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter

(0/1/2/3)

Off

LCD Display

Enable

Pull-high of TMR0/TMR1 With pull-high resistor

Input/output Ports

Input mode

Points to the top of the

stack

R E S

V D D

Reset circuit

W D T

H A L T

W D T

T i m e - o u t

R e s e t

R E S

C o l d

R e s e t

W a r m R e s e t

P o w e r - o n D e t e c t i n g

S S T

1 0 - s t a g e

R i p p l e C o u n t e r

O S C I

Reset configuration

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset timing chart

The state of the registers is summarized in the following table:

Reset

(power on)

WDT time-out

(normal operation)

RES reset

(normal operation)

RES reset

(HALT)

WDT time-out

(HALT)*

TMR1H

xxxx xxxx

uuuu uuuu

TMR1L

xxxx xxxx

uuuu uuuu

TMR1C

00-0 1---

uu-u u---

TMR0H

xxxx xxxx

uuuu uuuu

HTG2190 Datasheet(PDF) 20 Page - Holtek Semiconductor Inc

HTG2190 Datasheet(HTML) 20 Page - Holtek Semiconductor Inc

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