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Revision History (Revision A)

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463B – SEPTEMBER 2007 – REVISED OCTOBER 2007

This data sheet revision history highlights the technical changes made to the SPRS463 device-specific

data sheet to make it an SPRS463A revision.

Scope:

Updated DM355 Pin Descriptions table, etc.

ADDS/CHANGES/DELETES

Section 1.1, Features:

•

Video Processing Subsystem feature:

–

14-Bit Parallel AFE (Analog Front End) Interface: Changed speed from 75 MHz to 67.5 MHz

Table 2-1, Characteristics of the Processor:

•

Corrected the Product Status

Updated Table 2-3, DM355 ARM Configuration Bus Access to Peripherals

Updated Figure 2-1, Pin Map [Quadrant A]

Updated Figure 2-2, Pin Map [Quadrant B]

Updated Figure 2-3, Pin Map [Quadrant C]

Updated Figure 2-4, Pin Map [Quadrant D]

Table 2-7, Digital Video Terminal Functions:

•

Changed Terminal No. of YOUT7-R7 from "C2" to "C3"

Table 2-9, Asynchronous EMIF/NAND/OneNAND Terminal Functions:

•

Changed Terminal No. of EM_BA0/GIO054/EM_A14 from "T19" to "N19"

•

H16: Changed Terminal Name from EM_AVD/GIO032 to EM_ADV/GIO032

Table 2-10, DDR Terminal Functions:

•

R11: Changed Terminal Name from DDR_VSSDLL to VSSA_DLL

•

R10: Changed Terminal Name from DDR_VDDDLL to VDDA33_DDRDLL

Updated Table 2-11, GPIO Terminal Functions

Section 2.4.7, Universal Serial Bus (USB) Interface:

•

Deleted NOTE about OTG supplies not being supported

Updated Table 2-13, USB Terminal Functions

Table 2-17, SPI Terminal Functions:

•

Changed Terminal No. of GIO007/SPI0_SDENA[1] from "B12" to "C17"

Table 2-21, System/Boot Terminal Functions:

•

Updated all Terminal Names — changed "GOP" to "GIO"

Updated Table 2-23, DM355 Pin Descriptions

Section 3.1.1, Components of the ARM Subsystem:

•

Updated the "Video Processing Front End (VPFE)" sub-list

Updated Table 3-7, PLL2 Supported Clocking Configurations for DM355-270 (24 MHz reference)

Table 3-9:

•

Changed title from "PLL2 Supported Clocking Configurations for DM355L (36 MHz reference)" to "PLL2 Supported Clocking

Configurations for DM355-270 (36 MHz reference)"

•

Updated table

Section 3.12.1, Boot Modes Overview:

•

"If BTSEL[1:0] = 01" bulleted item: Changed "Asynchronous EMIF (AEMIF or NOR Flash) boot." to "Asynchronous EMIF (AEMIF)

boot."

Section 4.2, Recommended Operating Conditions:

•

Changed VDD_PLL1 to VDDA_PLL1

•

Changed VDD_PLL2 to VDDA_PLL2

•

Added VDDA33_DDRDLL (Supply voltage, DDR DLL Analog)

•

Removed VDDA18 (Supply voltage, Analog)

•

Changed VSSA_USB to VSS_USB

•

Removed VSSA (Supply ground, Analog)

•

Updated descriptions of VSS_MX1 and VSS_MX2

Revision History (Revision A)

154

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