CD2481 datasheet(7/222 Pages) INTEL

7 / 222 page

Datasheet

Programmable Four-Channel Communications Controller — CD2481

DMA Connections for the CD2481 ...................................................................... 68

Character Format ................................................................................................ 77

Point-to-Point Protocol Frame ............................................................................. 77

ARAP 1.0 Frame ................................................................................................. 83

ARAP 2.0 Frame ................................................................................................. 83

CD2481 Receive Character Processing.............................................................. 89

Initialization Sequence for the CD2481 .............................................................104

CLK / BUSCLK / RESET* Timing Relationship.............................................. 206

Slave Read Cycle Timing .................................................................................. 207

Slave Write Cycle Timing .................................................................................. 208

Interrupt Acknowledge Cycle Timing................................................................. 209

Bus Arbitration Cycle Timing ............................................................................. 210

Bus Release Timing .......................................................................................... 211

Bus Release Timing .......................................................................................... 212

DMA Read Cycle Timing ................................................................................... 213

DMA Write Cycle Timing ................................................................................... 214

Tables

Pin Descriptions .................................................................................................. 17

Transmit and Receive Interrupt Service Requests.............................................. 42

A and B Buffers and Chaining ............................................................................. 48

Clock Source Select ............................................................................................ 62

Bit Rate Constants, CLK = 25 MHz .....................................................................63

Bit Rate Constants, CLK = 30 MHz .....................................................................63

Bit Rate Constants, CLK = 35 MHz .....................................................................64

Bit Rate Constants, CLK = 60 MHz .....................................................................64

Data Clock Selection Using External Clock......................................................... 67

DTE Connections ................................................................................................ 68

DCE Connections................................................................................................ 69

Special Character Definition................................................................................ 82

SSPC[x] Settings................................................................................................. 87

SCdet[x] Settings................................................................................................. 87

Bisync Receive State Transition (see “Key” on page 96)................................... 95

ETC Byte Sequence............................................................................................ 97

Byte Format - ETC Bit Set................................................................................... 99

CD2481 Datasheet(PDF) 7 Page - Intel Corporation