CD2481 datasheet(42/222 Pages) INTEL

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CD2481 — Programmable Four-Channel Communications Controller

Datasheet

5.2.4

Hardware Signals and IACK Cycles

The IACK (interrupt acknowledge) bus cycle begins with the IACKIN* (Interrupt Acknowledge

In) and DS* asserted, and a value matching the appropriate PILR contents on the least-significant

seven address bus bits, A[6:0]. If the IACK cycle is valid (that is, the A[6:0] and PILR values

match), the corresponding vector from the interrupting channels LIVR is driven onto the data bus

and DTACK* asserted. DTACK* is released after DS* is removed.

Figure 4 shows the interrupt acknowledge cycle timing. It is similar to the basic host read cycle

except that IACKIN* is active, and CS* is inactive.

The three IREQn* pins are open-drain outputs requiring external pull-up resistors, nominally 4.7

Ω. The IACKOUT* (Interrupt Acknowledge Out) is used to form a daisy-chain in systems with

more than one CD2481.

5.2.4.1

Programming the PILR Registers

The three PILRs must be programmed with values that correspond to the least-significant seven

address bits that will be present on A[6:0] during the interrupt acknowledge bus cycle. Some CPUs

output the priority level of the interrupt that is being acknowledged on the bus during the IACK

cycle. In these systems the three PILR values are unique. In other systems that do not use this

scheme, the PILR values can be the same or different depending on the specific design. When all of

Table 2.

Transmit and Receive Interrupt Service Requests

Interrupt Cause

Async

HDLC

Bisync

X.21

PPP

SLIP

MNP4

Receive Good Data

 1

1.Non-DMA mode

••

•

Break detect

••

•

Framing error

••

•

Parity error

••

•

Receive time-out, no data

••

•

Special character match

••

•

Transmitter empty

••

•

Tx FIFO threshold a

••

•

Receive overrun

••

•

Clear detect

•

CRC error

••

•

Residual bit count

•

Receive abort

••

•

End of frame

••

•

Transmit underrun

•

Bus error 2

2.DMA mode only

••

•

End of buffer b

••

•

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