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CD2481 Datasheet(PDF) 1 Page - Intel Corporation |
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CD2481 Datasheet(HTML) 1 Page - Intel Corporation |
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1 / 222 page  CD2481 Programmable Four-Channel Communications Controller Datasheet The CD2481 is a four-channel synchronous/asynchronous communications controller specifically designed to reduce host-system processing overhead and increase efficiency in a wide variety of communications applications. A special member of the CD24X1 family, the device allows easy field upgrades and enhancement with an on-chip 8K-word microcode store for downloaded control code. The CD2481 is packaged in a 100-pin MQFP package that offers 10 data/clock/modem pins per channel. The device has four fully independent serial channels to support standard asynchronous, PPP, MNP4, SLIP, bit-synchronous (HDLC), and byte- synchronous (bisync, X.21) protocols. The device is non-functional until the microcode is downloaded; only a small boot ROM with code to perform device initialization is included. The device is based on a proprietary on-chip RISC processor that performs all the time-critical, low-level tasks otherwise performed by the host system. The CD2481 boosts system efficiency with eight on-chip DMA channels, on-chip FIFOs (16 bytes/direction), intelligent vectored interrupts, and intelligent protocol processing. The on-chip DMA controller provides ‘fire-and-forget’ transmit support — the host need only inform the CD2481 of the location of the packet to send. Similarly, on receive, the CD2481 automatically receives a complete packet with no host intervention or assistance. The DMA controller also has a transmit ‘Append mode’ for use in asynchronous applications. The DMA controller uses a dual-buffer scheme that easily implements simple or complex buffer schemes. Each channel and direction in the dual-buffer scheme has two active buffers. The CD2481 can be programmed to interrupt the host at the completion of a frame or buffer. In applications where buffers are of a small, fixed size, the dual-buffer scheme allows large frames to be divided into multiple buffers. For applications where a DMA interface is not desired, the device can be operated as either interrupt-driven or polled. This choice is available for each channel and each direction. For example, a channel can be programmed for DMA transmit and interrupt-driven receive. In either case, 16-byte FIFOs on each channel and in each direction reduce latency time requirements, making both software and hardware designs less time-critical. Threshold levels on the FIFOs are user-programmable. Vectored interrupts are another way the CD2481 helps system efficiency. Separate interrupts are generated for transmit, receive, and modem-signal/timer changes with unique, user-defined vectors for each type and channel. This allows very flexible interfacing and fast, efficient interrupt coding. For example, the Good Data interrupt allows the host to vector directly to a routine that transfers the receive data — no status or error checking is required. As of May 2001, this document replaces the Basis Communications Corp. document CL-CD2481 — Programmable Four-Channel Communications Controller. May 2001 |
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