29PL256N datasheet(35/74 Pages) SPANSION

35 / 74 page

June 6, 2007 S29PL-N_00_A5

S29PL-N MirrorBit

™ Flash Family

Da ta

Shee t

(Prelim i nar y )

7.4.7

Accelerated Program

Accelerated single word programming, write buffer programming, sector erase, and chip erase operations are

enabled through the ACC function. This method is faster than the standard chip program and erase command

sequences.

The accelerated chip program and erase functions must not be used more than 10 times per sector.

In addition, accelerated chip program and erase should be performed at room temperature (25

°C ±10°C).

This function is primarily intended to allow faster manufacturing throughput at the factory. If the system

asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses

the higher voltage on the input to reduce the time required for program and erase operations. The system can

then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a

Write-to-Buffer-Abort Reset is required while in Unlock Bypass mode, the full 3-cycle RESET command

sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the

embedded program or erase operation, returns the device to normal operation.

Sectors must be unlocked prior to raising WP#/ACC to VHH.

The WP#/ACC must not be at VHH for operations other than accelerated programming and accelerated

chip erase, or device damage can result.

Set the ACC pin at VCC when accelerated programming not in use.

7.4.8

Unlock Bypass

The device features an Unlock Bypass mode to facilitate faster word programming. Once the device enters

the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal four

cycles.

This mode dispenses with the initial two unlock cycles required in the standard program command sequence,

resulting in faster total programming time. Table 12.1, Memory Array Commands on page 66 shows the

requirements for the unlock bypass command sequences.

During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset

commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass

reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle

need only contain the data 00h. The bank then returns to the read mode.

29PL256N Datasheet(PDF) 35 Page - SPANSION