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29PL256N Datasheet(PDF) 63 Page - SPANSION |
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29PL256N Datasheet(HTML) 63 Page - SPANSION |
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63 / 74 page ![]() June 6, 2007 S29PL-N_00_A5 S29PL-N MirrorBit ™ Flash Family 63 Da ta Shee t (Prelim i nar y ) Figure 11.11 Chip/Sector Erase Operation Timings Note SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 37) Figure 11.12 Back-to-back Read/Write Cycle Timings OE# CE# Addresses VCC WE# Data 2AAh SA tAH tWP tWC tAS tWPH 555h for chip erase 10 for Chip Erase 30h tDS tVCS tCS tDH 55h tCH Status DOUT tWHWH2 VA VA Erase Command Sequence (last two cycles) Read Status Data RY/BY# tRB tBUSY OE# CE# WE# Addresses tOH Data Valid In Valid In Valid PA Valid RA tWC tWPH tAH tWP tDS tDH tAS tRC tCE tAH Valid Out tOE tACC tOEH tGHWL tDF Valid In CE# Controlled Write Cycles WE# Controlled Write Cycle Valid PA Valid PA tCP tCPH tWC tWC Read Cycle tSR/W tAS |
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