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29PL256N Datasheet(PDF) 73 Page - SPANSION |
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29PL256N Datasheet(HTML) 73 Page - SPANSION |
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73 / 74 page ![]() June 6, 2007 S29PL-N_00_A5 S29PL-N MirrorBit ™ Flash Family 73 Da ta Shee t (Prelim i nar y ) 14. Revision History Section Description Revision A0 (February 28, 2005) Initial release Revision A1 (August 8, 2005) Performance Characteristics Updated Package Options MCP Look-Ahead Connection Diagram Corrected pinout Memory Map Added Sector and Memory Address Map for S29PL127N Device Operation Table Added Dual Chip Enable Device Operation Table VCC Power Up Updated tVCS. Added VCC ramp rate restriction DC Characteristics Updated typical and maximum values. Revision A2 (October 25, 2005) Ordering Information Updated table Connection Diagram and Package Dimensions - S29PL-N Fortified BGA Added pinout and package dimensions. Global Changed data sheet status from Advance Information to Preliminary. Removed Byte Address Information Distinctive and Performance Characteristics Removed Enhanced VersatileI/O, updated read access times, and Package options. Logic Symbol and Block Diagram Removed VIO from Logic Symbol and Block Diagram. Erase and Programming Performance Updated table Write Buffer Programming Updated Write Buffer Abort Description. Operating Ranges Updated VIO supply voltages. DC characteristics Updated ICC1, ICC4, ICC6. Revision A3 (November 14, 2005) Ordering Information Updated table Valid Combinations Table Updated table Revision A4 (November 23, 2005) Logic Symbols Removed VIO from the illustrations Block Diagram Removed VIO from the illustration Connection Diagrams Modified Fortified BGA Pinout (LAA064) PL129N Sector and Memory Address Map Updated Address Ranges for Banks 2A and 2B Revision A5 (June 6, 2007) Global Removed LAA064 package offering and all relevant ordering information |
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