UJA1069 datasheet(21/64 Pages) NXP

21 / 64 page

UJA1069_3

Product data sheet

Rev. 03 — 10 September 2007

21 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.7.5 LIN driver capability

Setting the LDC bit in the Physical Layer Control register will increase the driver capability

of the LIN output stage. This feature is used in auto-addressing systems, where the

standard LIN 2.0 drive capability is insufﬁcient.

6.7.6 Bus and TXDL failure detection

The SBC handles and reports the following LIN-bus related failures:

• LIN-bus shorted to ground

• LIN-bus shorted to VBAT14 or VBAT42; the transmitter is disabled

• TXDL clamped dominant; the transmitter is disabled

These failure events force an interrupt to the microcontroller whenever the status changes

and the corresponding interrupt is enabled.

6.7.6.1

TXDL dominant clamping

If the TXDL pin is clamped dominant for longer than tTXDL(dom)(dis) the LIN transmitter is

disabled. After the TXDL pin becomes recessive the transmitter is reactivated

automatically when detecting bus activity or manually by setting and clearing the LTC bit.

6.7.6.2

LIN dominant clamping

When the LIN-bus is clamped dominant for longer than tLIN(dom)(det) (which is longer than

tTXDL(dom)(dis)), the state of the LIN termination is changed according to Figure 11.

6.7.6.3

LIN recessive clamping

If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter

is disabled. The transmitter is reactivated automatically when the LIN bus becomes

dominant or manually by setting and clearing the LTC bit.

6.8 Inhibit and limp-home output

The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for

an extra (external) voltage regulator, or as a ‘limp-home’ output. The pin is controlled via

the ILEN bit and ILC bit in the System Conﬁguration register; see Figure 12.

UJA1069 Datasheet(PDF) 21 Page - NXP Semiconductors