TMPR4951B datasheet(112/256 Pages) TOSHIBA

112 / 256 page

Chapter 5 Cache Organization

5-10

5.10 Cache Operations

As described earlier, caches provide fast temporary data storage, and they make the speedup of memory

accesses transparent to the user. In general, the processor accesses cache-resident instructions or data through

the following procedure:

1. The processor, through the on-chip cache controller, attempts to access the next instruction or data in

the appropriate cache.

2. The cache controller checks to see if this instruction or data is present in the cache.

•

If the instruction/data is present, the processor retrieves it. This is called a cache

hit.

•

If the instruction/data is not present in the cache, the cache controller must retrieve it from memory.

This is called a cache

miss.

3. The processor retrieves the instruction/data from the cache and operation continues.

It is possible for the same data to be in two places simultaneously: main memory and cache. This data is

kept consistent through the use of a

write-back methodology; that is, modified data is not written back to

memory until the cache line is to be replaced.

Instruction and data cache line replacement operations are listed in described as the following sections.

Table 5.10.1 Cache Instruction

Name

Caches

Operation

Index Invalidate

Instruction

Sets the cache state of cache block to invalid.

Index Write Back Invalidate

Data

Examines cache state, if Valid Dirty, then that block is written back to

main memory. Then the cache block is set to invalid.

Index Load Tag

Instruction & Data

Read the tag for the cache block at the specified index and place it into

TagLo.

Index Store Tag

Instruction & Data

Write the tag for the cache block at the specified index from the TagLo and

TagHi register.

Create Dirty Exclusive

Data

If the cache does not contain the specified address, and the block is Valid

Dirty the block will be written back to main memory. Then the tag will be

set to the specified physical address and will be marked valid.

Hit Invalidate

Instruction & Data

If the cache block contains the specified address, cache block will be

marked invalid.

Hit Write Back Invalidate

Data

If the cache block contains the specified address, and it is Valid Dirty, the

data will be written back to main memory. Then, the cache block is

marked invalid.

Fill

Instruction

Fill the Instruction cache block from main memory.

Fill

Data

Fill the Data cache block from memory.

Hit Write Back

Data

If the cache block contains the specified address, and it is marked Valid

Dirty, the block will be written back to main memory, and marked Valid

Clean.

TMPR4951B Datasheet(PDF) 112 Page - Toshiba Semiconductor

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