TMPR4951B datasheet(113/256 Pages) TOSHIBA

113 / 256 page

Chapter 5 Cache Organization

5-11

5.10.1

Cache Write Policy

The TX4951B processor manages its data cache by using a write-back and a write-through policy. A

write-back stores write data into the cache, instead of writing it directly to memory. Some time later this

data is independently written into memory. In the TX4951B implementation, a modified cache line is

not written back to memory until the cache line is to be replaced either in the course of satisfying a

cache miss, or during the execution of a write-back CACHE instruction.

When the processor writes a cache line back to memory, it does not ordinarily retain a copy of the

cache line, and the state of the cache line is changed to invalid.

A write-through is written simultaneously to cache and memory.

5.10.2

Data Cache Line Replacement

Since the data cache uses a write-back and a write-through methodology, a cache line load is issued

to main memory on a load or store miss, as described below. After the data from memory is written to

the data cache, the pipeline resumes execution.

TX4951B does not support “Critical Data Word First”. Always it transfer the data of first address.

Rules for replacement on data load and data store misses are given below.

•

Data Load Miss

If the missed line is not dirty, it is replaced with the requested line.

If the missed line is dirty, it is moved to the write buffer. The requested line replaces the missed

line, and the data in the write buffer is written to memory.

•

Data Store Miss

If the missed line is not dirty, the requested line is merged with the store data and written to

memory.

If the missed line is dirty, it is moved to the write buffer. The requested line is merged with the

store data and written to cache, and data in the write buffer is written to memory.

The data cache miss penalties, in number of GBUSCLK cycles, are given in Table 5.10.2.

Table 5.10.2 Data Cache Refill Penalty Cycle Count

Number of

CPUCLK Cycles

Action

Stall the DC stage.

Transfer address to the write buffer and wait for the pipeline start signal

1-2

Transfer address to the internal SysAD bus on the GBUSCLK.

Transfer to the external SysAD bus.

Time needed to access memory, measured in CPUCLK cycles.

Transfer the cache line form memory to the SysAD bus.

Transfer the cache line from the external bus to the internal bus.

Restart the DC stage.

TMPR4951B Datasheet(PDF) 113 Page - Toshiba Semiconductor

TMPR4951B Datasheet(HTML) 113 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL