TMPR4956C datasheet(73/286 Pages) TOSHIBA

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Chapter 3 TX49/H4 Core’s Registers

3-13

3.2.11

Status Register (Reg

#12)

The Status register is a read/write register that contains the operating mode, interrupt enabling, and

diagnostic states of the processor. The more important Status register fields are as followings:

•

The Interrupt Mask (IM) field of 8 bits controls the enabling of eight interrupt conditions.

Interrupt must be enabled before they can be asserted, and the corresponding bits are set in both

the IM field of this register and the Interrupt Pending field of the Cause register.

•

The Coprocessor Usability (CU) field of 4 bits controls the usability of four possible

coprocessors. Regardless of the CU0 bit setting, CP0 is always usable in Kernel mode.

•

The Diagnostic Status (DS) field of 9 bits is used for self-testing, and checks the cache and

virtual memory system.

•

The Reverse Endian (RE) bit reverses the endianness. The processor can be configured as either

little/big-endian at reset; reverse-endian selection is used in Kernel and Supervisor modes, and

in the User mode when the RE bit is 0. Setting the RE bit to 1 inverts the User mode endianness.

Figure 3.2.11 shows the format of the Status register and Table 3.2.12 describes the Status register field.

16 15

KSU

ERL

EXL

24 23

BEV

Figure 3.2.11 Status Register Format

Table 3.2.12 Status Register Field Descriptions

Bit(s)

Field Name

Description

Cold Reset

Read/Write

31:28

(3, 2, 1, 0)

Controls the usability of each of the four coprocessor unit

numbers. CP0 is always usable when in Kernel mode,

regardless of the setting of the CU0 bit.

0: unusable

1: usable

0000

Read/Write

Reserved

Read

Number of floating-point registers(FPR)

0: 64-bit wide 16 FPRs

1: 32-bit wide 32 FPRs

See Section 3.3.1, “Floating-Point General Registers” in

detail.

Read/Write

Reverse-Endian bit, valid in User mode.

Read/Write

24:23

Reserved

0x0

Read

BEV

Controls the location of TLB refill and general exception

vectors.

0: normal

1: bootstrap

Read/Write

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