TMPR4956C datasheet(95/286 Pages) TOSHIBA

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Chapter 4 Memory Management System

4-1

Memory Management System

The processor provides a full-featured memory management unit (MMU) which uses an on-chip translation

look aside buffer (TLB) to translate virtual addresses into physical addresses.

4.1

Address Space Overview

The physical address space is either 4 Gbytes or 64 Gbytes depending on whether the processor is operating

in 32- or 64-bit bus width mode. In 32-bit bus width mode, address space is 4 Gbytes using a 32-bit address. In

64-bit bus width mode, address space is 64 Gbytes using a 36-bit address.

The virtual address is either 32 or 64 bits wide depending on whether the processor is operating in 32- or

64-bit bus width mode. In 32-bit bus width mode, addresses are 32 bits wide and the maximum user process

size is 2 Gbytes (2

31). In 64-bit bus width mode, addresses are 64 bits wide and the maximum user process is 1

Tbytes (2

40). The virtual address is extended with an Address Space Identifier (ASID) to reduce the frequency

of TLB flushing when switching context. The size of the ASID field is 8 bits. The ASID is contained in the

CP0 EntryHi register.

4.1.1

Virtual Address Space

The processor virtual address can be either 32 or 64 bits wide, depending on whether the processor is

operating in 32-bit or 64-bit bus width mode.

•

In 32-bit bus width mode, addresses are 32 bits wide.

The maximum user process size is 2 Gbytes (2

31).

•

In 64-bit bus width mode, addresses are 64 bits wide.

The maximum user process size is 1 Tbytes (2

40).

Figure 4.1.1 shows the translation of a virtual address into a physical address.

Figure 4.1.1 Overview of a Virtual-to-Physical Address Translation

As shown in Figure 4.1.2 and Figure 4.1.3, the virtual address is extended with an 8-bit address space

identifier (ASID), which reduces the frequency of TLB flushing when switching contexts. This 8-bit

ASID is in the CP0 EntryHi register, described later in this chapter. The Global bit (G) is in the EntryLo0

and EntryLo1 registers, described later in this chapter.

The Offset, which does not pass through the

TLB, is then concatenated to the PFN.

If there is a match, the page frame number

(PFN) representing the upper bits of the

physical address (PA) is output from the

TLB.

Physical address

Virtual address

Virtual address (VA) represented by the

virtual page number (VPN) is compared with

tag in the TLB.

VPN

ASID

VPN

ASID

PFN

TLB

Offset

PFN

TLB

Entry

Offset

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