TMPR4956C datasheet(99/286 Pages) TOSHIBA

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Chapter 4 Memory Management System

4-5

4.2

Operating Modes

The processor has the three operating modes, User mode, Supervisor mode and Kernel mode, for 32- and

64-bit operation. The KSU, EXL and ERL bit in the Status register select User, Supervisor or Kernel mode.

The UX, SX and KX bit in the Status register select 32- or 64-bit addressing in user, supervisor and kernel

mode respectively.

KSU

EXL

ERL

Mode

–

32-bit addressing in user mode

–

64-bit addressing in user mode

–

32-bit addressing in supervisor mode

–

64-bit addressing in supervisor mode

–

32-bit addressing in kernel mode

–

32-bit addressing in kernel mode

–

32-bit addressing in kernel mode

–

64-bit addressing in kernel mode

–

64-bit addressing in kernel mode

–

64-bit addressing in kernel mode

4.2.1

User Mode Operations

In User mode, a single, uniform virtual address space-labelled User segment-is available; its size is:

•

2 Gbytes (2

31 bytes) in 32-bit mode (useg)

•

1 Tbytes (2

40 bytes) in 64-bit mode (xuseg)

Figure 4.2.1 shows User mode virtual address space.

Figure 4.2.1 User Mode Virtual Address Space

Note:

In 32-bit mode, bit 31 is sign-extended through bits 63-32. Failure results in an address

error exception.

The User segment starts at address 0 and the current active user process resides in either useg (in 32-bit

mode) or xuseg (in 64-bit mode). The TLB identically maps all references to useg/xuseg from all modes,

and controls cache accessibility.

The processor operates in User mode when the Status register contains the following bit-values:

•

KSU bits = 102

•

EXL = 0

•

ERL = 0

0x 0000 0000 0000 0000

0x 0000 0100 0000 0000

0x FFFF FFFF FFFF FFFF

xuseg

useg

0x 0000 0000

0x 8000 0000

0x FFFF FFFF

64-bit

32-bit

(Note)

2 GB

Mapped

Cacheable

Address

Error

1 TB

Mapped

Cacheable

Address

Error

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