TMPR4956C datasheet(89/286 Pages) TOSHIBA

89 / 286 page

Chapter 3 TX49/H4 Core’s Registers

3-29

3.3

Floating-Point Unit, CP1

The floating-point operations fully conform to the requirements of ANSI/IEEE Standard 754-1985, IEEE

Standard for Binary Floating-Point Arithmetic

3.3.1

Floating-Point General Registers (FGRs)

CP1 has a set of Floating-Point General Purpose registers (FGRs) that can be accessed in the following

ways:

•

As 32 general purpose registers (32 FGRs), each of which is 32-bits wide when the FR bit in the

CPU Status register equals 0; or as 32 general purpose registers (32 FGRs), each of which is

64-bits wide when FR equals 1. The CPU accesses these registers through move, load, and store

instructions.

•

As 16 floating-point registers (see the next section for a description of FPRs), each of which is

64-bits wide, when the FR bit in the CPU Status register equals 0. The FPRs hold values in

either single- or double-precision floating-point format. Each FPR corresponds to adjacently

numbered FGRs as shown in Figure 3.3.1.

•

As 32 floating-point registers (see the next section for a description of FPRs), each of which is

64-bits wide, when the FR bit in the CPU Status register equals 1. The FPRs hold values in

either single- or double-precision floating-point format. Each FPR corresponds to an FGR as

shown in Figure 3.3.1.

Floating-point

Registers (FPR)

(FR

= 0)

Floating-Point

General Purpose Registers

Floating-point

Registers (FPR)

(FR

= 1)

Floating-Point

General Purpose Registers

(FGR)

(least)

FGR0

FPR0

FGR0

FPR0

(most)

FGR1

FPR1

FGR1

(least)

FGR2

FPR2

FGR2

FPR2

(most)

FGR3

FPR3

FGR3

•

(least)

FGR28

FPR28

FGR28

FPR14

(most)

FGR29

FPR29

FGR29

(least)

FGR30

FPR30

FGR30

FPR15

(most)

FGR31

FPR31

FGR31

Floating-point

Control Registers

(FCR)

Control/Status Register

Implementation/Revision Register

(FCR31)

(FCR0)

Figure 3.3.1 FP Registers

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