TMPR4956C datasheet(79/286 Pages) TOSHIBA

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Chapter 3 TX49/H4 Core’s Registers

3-19

3.2.15

Config Register (Reg

#16)

The Config register is a read-only register; except for HALT, ICE

#, DCE# and K0 fields. This register

specifies various configuration options selected on the processor.

EC, BE, IC, DC, IB and DB fields are set by the hardware during reset and are included in this register

as read-only status bits for the software to access.

Figure 3.2.15 shows the format of the Config register and Table 3.2.16 describes the Config register

field.

28 27

24 23

14 13

9 8

HALT

ICE

DCE

Figure 3.2.15 Config Register Format

Table 3.2.16 Config Register Field Descriptions

Bit(s)

Field Name

Description

Cold Reset

Read/Write

Reserved

Read

30:28

GBUS clock rate

This bit indicates the divided rate of CPUCLK and GBUSCLK.

0: processor clock frequency divided by 2

1: processor clock frequency divided by 3

2: processor clock frequency divided by 4

3: processor clock frequency divided by 6

4: processor clock frequency divided by 3.5

5: processor clock frequency divided by 4.5

6: processor clock frequency divided by 5

7: processor clock frequency divided by 2.5

Read

27:19

Reserved

0x0

Read

HALT

Wait mode

0: Halt

1: Doze

Indicates the power-down behavior of the processor when

WAIT instruction is executed. The processor stalls the

pipeline both in halt and doze mode. Cache snoops are

possible during Doze mode but not possible during Halt

mode. Halt mode reduces power consumption to a greater

extent than Doze mode.

Read/Write

ICE

Instruction Cache Enable

0: Instruction cache enable

1: Instruction cache disable

Read/Write

DCE

Data Cache Enable

0: Data cache enable

1: Data cache disable

Read/Write

Big Endian

0: Little Endian

1: Big Endian

Read

14:13

Reserved

Read

Reserved

Read

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