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TMPR4956C Datasheet(PDF) 86 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 86 Page - Toshiba Semiconductor

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Chapter 3 TX49/H4 Core’s Registers
3-26
3.2.20
TagLo Register (Reg
#28) and TagHi Register (Reg#29)
The TagLo and TagHi registers are a read/write registers. These registers hold the primary cache tag for
cache lock function or cache diagnostics. These registers are written by the CACHE/MTC0 instruction.
Figure 3.2.20 shows the formats of the TagLo and TagHi registers and Table 3.2.21 describes the TagLo
and TagHi registers field.
31
8 7
6 5
3
2
1
0
PTagLo
PState
RWNT
Lock
F0
0
(TagLo)
31
30
29
0
F1
PTagLo1
0
(TagHi)
Figure 3.2.20 TagLo and TagHi Register Formats
Table 3.2.21 TagLo and TagHi Register Field Descriptions
TagLo
Bit(s)
Field Name
Description
Cold Reset
Read/Write
31:8
PTagLo
Bits 35-12 of the physical address
0x0
Read/Write
7:6
PState
Specifies the primary cache state
0: Invalid
1: Reserved
2: Reserved
3: Valid
0x0
Read/Write
5:3
RWNT
Read/Write bits required for Windows NT
0x0
Read/Write
2
Lock
Lock bit (0: not locked, 1: locked)
0
Read/Write
1
F0
FIFO Replace bit 0 (indicates the set to be replaced)
0
Read/Write
0
0
Reserved
0
Read
TagHi
Bit(s)
Field Name
Description
Cold Reset
Read/Write
31
F1
FIFO Replace bit 1 (indicates the set to be replaced)
0
Read/Write
30
PTagLo1
Bit 11 of the physical address
0
Read/Write
29:0
0
Reserved
0x0
Read
F1 and F0 are concatenated and indicate the set to be replaced.
F1
⏐ F0
0
0
: way0
0
1
: way1
1
0
: way2
1
1
: way3



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