TMPR4956C datasheet(97/286 Pages) TOSHIBA

97 / 286 page

Chapter 4 Memory Management System

4-3

4.1.4

32-bit Mode Address Translation

Figure 4.1.2 shows the virtual-to-physical-address translation of a 32-bit mode address. This figure

illustrates two of the possible page sizes: a 4-Kbyte page (12 bits) and a 16-Mbyte page (24 bits).

•

The top portion of Figure 4.1.2 shows a virtual address with a 12-bit, or 4-Kbyte, page size,

labeled Offset. The remaining 20 bits of the address represent the VPN, and Index the 1M-entry

page table.

•

The bottom portion of Figure 4.1.2 shows a virtual address with a 24-bit, or 16-Mbyte, page size,

labeled Offset. The remaining 8 bits of the address represent the VPN, and index the 256-entry

page table.

Figure 4.1.2 32-bit Mode Virtual Address Translation

Offset passed

unchanged to

physical

memory

Offset passed

unchanged to

physical

memory

Virtual-to-physical

translation in TLB

Bits 31, 30 and 29 of the virtual

address select user, supervisor,

or kernel address spaces.

Virtual-to-physical

translation in TLB

Virtual Address with 256 (2

8) 16-Mbyte pages

Virtual Address with 1M (2

20) 4-Kbyte pages

TLB

20 bits = 1 M pages

VPN

ASID

32 31

Offset

32-bit Physical Address

PFN

Offset

8 bits = 256 pages

VPN

ASID

32 31

Offset

TLB

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