TMP88CS38 datasheet(131/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-131

2.13.2

PWM Output Wave Form

(1) PWM0 to PWM1 Outputs

PWM0

and PWM1 output can be selected 12-bit or 14-bit resolution PWM outputs.

1. 12-bit resolution PWM output

When these are used as 12-bits PWM output, one period is TM = 213/fc [s] (When

DV1CK

= 0) and TM = 214/fc [s] (When DV1CK = 1) and sub period is TS = TM/16.

The lower 8 bits of the PWM data latch controls the low level pulse width with a

cycle of TS. The lower 8 bits of the PWM data latch is n (n = 1 to 255), the low level

pulse width with a cycle becomes n

× t0 [s] (t0 = 2/fc [s] when DV1CK = 0, t0 = 4/fc

[s] when DV1CK

= 1).

The upper 4 bits of the PWM data latch controls a position to output the

additional pulses. When the upper 4 bits of the PWM data latch is m, the

additional pulses are generated in each of m periods out of 16 periods contained in

a TM period.

The relationship between the 4-bit data and the position of TS period where the

additional pulses are generated is shown in Table 2.13.1.

Table 2.13.1 The Addition Pulse (12-bit mode)

Bit Position of the Lower 4 Bits of PWMDRxH

Bit11

Bit10

Bit9

Bit8

Relative position of TS in TM period where the additional

pulse is generated. (Number of TS (I) is listed)

No additional pulse

4, 12

2, 6, 10, 14

1, 3, 5, 7, 9, 11, 13, 15

Note 1:

The bit positions of a) to e) can be combined.

Note 2:

If the low order eight bits for the PWM data latch are set to “FFH”, be sure to set the high order

four bits for this latch to “00H”.

2. 14-bit resolution PWM output

When these are used as 14-bit PWM output, one period is TM = 215/fc [s] (When

DV1CK

= 0) and TM = 216/fc [s] (When DV1CK = 1) and sub period is TS = TM/64.

The lower 8 bits of the PWM data latch controls the low level pulse width with a

cycle of TS. The lower 8 bits of the PWM data latch is n (n = 1 to 255), the low level

pulse width with a cycle becomes n

× t0 [s] (t0 = 2/fc [s] when DV1CK = 0, t0 = 4/fc

[s] when DV1CK

= 1).

The upper 6 bits of the PWM data latch controls a position to output the

additional pulses. When the upper 6 bits of the PWM data latch is m, the

additional pulses are generated in each of m periods out of 64 periods contained in

a TM period.

The relationship between the 6-bit data and the position of TS period where the

additional pulses are generated is shown in Table 2.13.2.

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