LTM4719 datasheet(39/53 Pages) AD

39 / 53 page

Data Sheet

LTM4719

analog.com

Rev. 0

39 of 53

If the resulting total resistance through the resistor chain (R1 + R2 + R3) is larger or smaller than desired, the choice

of R3 can be adjusted in the appropriate direction, and the calculation for R2 and R1 can be repeated.

Input Hold-Up Capacitance

The LTM4719 features internal micropower UVLO comparators that minimize the quiescent current required by the

application. However, due to their low operating current, the UVLO comparators exhibit a significant delay when

responding to an undervoltage condition. Sufficient input hold-up capacitance must be provided to ensure the

voltage on the utilized channel remains sufficient to power the buck converter until the transition to the secondary

channel is completed.

Consider the example illustrated in Figure 23 where the LTM4719 is being powered by the priority input (VIN1) at 12.8V

and the UVLO threshold on the VIN1 channel is programmed to 10V. At time t1, the priority input is unplugged, and the

buck converter begins discharging the input capacitor. At time t2, the UVLO threshold is reached, but the buck

converter remains operating from the priority channel due to the comparator delay. At time t3, after comparator

delay tDELAY, the buck converter switches over to the secondary input (VIN2), and the input capacitor on VIN1 maintains

its voltage since there is no longer any current being drawn on that channel. In this example, the input capacitor on

VIN1 must be large enough that VIN1 remains at sufficient voltage to maintain the output voltage in regulation until

time t3. If VIN1 is allowed to drop lower than the regulated output voltage, then the buck converter output temporarily

loses regulation during the transition.

Figure 23. Waveforms During Transition from VIN1 to VIN2

Soft Start

The LTM4719 incorporates an internal soft start circuit with a nominal duration of 7.5ms. The soft start is

implemented by a linearly increasing ramp of the error amplifier reference voltage during the soft start duration. As

a result, the duration of the soft start period is largely unaffected by the size of the bus capacitor or the bus regulation

voltage. Given the closed-loop nature of the soft start implementation, the converter can respond to load transients

that occur during the soft start interval. The soft start period is reset by thermal shutdown, when the buck converter

is disabled through the EN1 pin, and when both inputs are in UVLO.

REF Output

The VREF output is a regulated, temperature-stable, 1V voltage reference. It is intended primarily to be used to

establish the VSET1 and VSET2 pin voltages. However, it can also be used for other functions if the total current drawn

from the pin is limited to 1mA or less. In addition to that restriction, there is also a maximum amount of capacitance

that can be placed on the VREF pin to maintain a suitable phase margin in the internal pin driver. The maximum

recommended capacitance on the VREF pin is 470pF or less. If the VREF pin is not being used in the application (i.e.,

there is no resistor from VREF to GND) then the VREF pin should be connected to INTVCC.

VIN1

IIN2

10V

tDELAY

LTM4719 Datasheet(PDF) 39 Page - Analog Devices