TPS65921 datasheet(32/70 Pages) TI2

32 / 70 page

TPS65921

SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014

www.ti.com

Table 4-8. Sequence Conversion Timing Characteristics

PARAMETER

COMMENTS

MIN

TYP

MAX

UNIT

Running frequency

MHz

T = 1/F

Clock period

μs

Number of analog inputs to convert in a

single sequence

Tstart

SW1, SW2, or USB asynchronous request

μs

or real-time STARTADC request

Tsettling time

Settling time to wait before sampling a

stable analog input (capacitor bank charge

time)

Tsettling is calculated from the max((Rs +

260

μs

Ron)*Cbank) of all possible input sources

(internal or external). Ron is the resistance

of the selection analog input switches (5

Ω). This time is software programmable by

OCP register; default value is 12 µs.

Tstartsar

The successive approximation registers

μs

ADC start time

Tadc time

The successive approximation registers

μs

ADC conversion time

Tcapture time

Tcapture time is the conversion result

μs

capture time.

Tstop

μs

Full Conversion

Only one channel (N = 1) (1)

μs

Sequence Time

All channels(2)

352

624

Conversion

Without Tstart and Tstop: Only one channel

Sequence Time

(N = 1) (1)

μs

Without Tstart and Tstop: All channels(1)

288

528

STARTADC pulse

STARTADC period is T

0.33

μs

duration

(1)

General-purpose input ADCIN0 must be tied to ground when TPS65921 internal power supplies (VINTANA1) is off.

(2)

Total Sequence Conversion Time General Formula: Tstart + N × (1 + Tsettling + Tadc + Tcapture) + Tstop.

Specifications

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