TPS65921 datasheet(36/70 Pages) TI2

36 / 70 page

JTAG.TCK

JTAG.TDI

JTAG.TMS

JTAG.TDO

JL1

JL2

JL7

JL3

JL4

JL6

JL5

SWCS048-007

TPS65921

SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014

www.ti.com

4.25 JTAG Interfaces

Table 4-11 and Table 4-12 assume testing over the recommended operating conditions.

Figure 4-7. JTAG Interface Timing

The input timing requirements are given by considering a rising or falling edge of 7 ns.

4.25.1 JTAG Interface Timing Requirements

Table 4-11. JTAG Interface Timing Requirements

NO.

PARAMETER

MIN

MAX

UNIT

Clock

JL1

tc(TCK)

Cycle time, JTAG.TCK period

JL2

tw(TCK)

Pulse duration, JTAG.TCK high or

0.48 × P

0.52 × P

low (1)

Read Timing

JL3

tsu(TDIV-TCKH)

Setup time, JTAG.TDI valid before

JTAG.TCK high

JL4

th(TDIV-TCKH)

Hold time, JTAG.TDI valid after

JTAG.TCK high

JL5

tsu(TMSV-TCKH)

Setup time, JTAG.TMS valid before

JTAG.TCK high

JL6

th(TMSV-TCKH)

Hold time, JTAG.TMS valid after

JTAG.TCK high

(1)

P = JTAG.TCK clock period

The capacitive load is equivalent to 35 pF.

Specifications

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