TPS65921 datasheet(41/70 Pages) TI2

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HFCLKIN

SLEEP1

CLKEN

Clock

generator

CLKREQ

Main state-machine

Optional request

configurable by software

only for legacy support

HFCLKOUT

Slicer

Timer

SLICER_OK

Slicer bypass

SWCS048-016

TPS65921

www.ti.com

SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014

The clock slicer is disabled by default and enabled when the CLKEN pad is high. The slicer transforms the

HFCLKIN clock input signal into a squared clock signal used internally by the TPS65921 device and also

outputs it for external use. The HFCLKIN input signal can be:

•

A sinusoid with peak-to-peak amplitude varying from 0.3 to 1.45 V

•

A square clock signal of amplitude 1.85 V maximum. In the case of a square clock signal, the slicer is

configured in bypass or power-down mode. If a square-wave input clock is provided, it is

recommended to switch the block to bypass mode when possible to avoid loading the clock.

The HFCLKIN input clock frequency must be 19.2, 26, or 38.4 MHz.

Four different modes are programmable by register. By default, the slicer is in high-performance

application mode:

•

Bypass mode (BP): In BP mode, which overrides all the other modes, the input signal is directly

connected to the output through some buffers. The input is a rail-to-rail square wave.

•

Power-down mode (PD): During PD mode, the cell does not consume any current if bypass mode is

not active.

•

Low-power application mode (LP): In LP mode, the input sine wave is converted to a CMOS signal

(square wave) with low power consumption.

•

High-performance application mode (HP): In HP mode, the input sine wave is converted to a CMOS

signal (square wave). It has lower duty cycle degradation and lower input-to-output delay in

comparison to the low-power mode, but it consumes more current. The drive of the squaring inverter is

increased by connecting additional inverters in parallel. Details can be found in the clock slicer

electrical characteristics table.

Figure 5-5 shows the HFCLKIN clock distribution.

Figure 5-5. HFCLKIN Clock Distribution

Detailed Description

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