TPS65921 datasheet(43/70 Pages) TI2

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TPS65921

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SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014

5.5

Power Path

5.5.1

Step-Down Converters

Depending on the system requirements, and also to optimize mean consumption, three operating modes

are allowed for each step-down converter:

•

Off/power-down mode: Output voltage is not maintained, and power consumption is null

•

Active: DC-DC can deliver its nominal output voltage with a full load current capability.

•

Sleep: The nominal output voltage is maintained with low power consumption, but also with a low load-

current capability.

The SMPS operates with three modulation schemes:

•

Light pulse frequency modulation (PFM)

•

Pulse skipping mode (PSM)

•

Continuous pulse-width modulation (PWM)

Each DC-DC converter, all of which have the same electrical characteristics, has an integrated RC

oscillator. The use of these RC oscillators is configurable through register bits, and by default the RC

oscillator of VDD1 is used for all DC-DC converters.

5.5.2

LDO

The VPLL1 programmable LDO regulator is high-PSRR, low-noise, linear regulator used for the host

processor PLL supply.

The VDAC programmable LDO regulator is a high-PSRR, low-noise, linear regulator that powers the host

processor dual-video DAC. It is controllable with registers through I2C and can be powered down.

The VMMC1 LDO regulator is a programmable linear voltage converter that powers the MMC slot. It

includes a discharge resistor and over-current protection (short circuit). This LDO regulator can also be

turned off automatically when the MMC card extraction is detected (through one dedicated GPIO). The

VMMC1 LDO can be powered through an independent supply other than the battery; for example, a

charge pump. In this case, the input from the VMMC1 LDO can possibly be higher than the battery

voltage.

The VAUX2 general-purpose LDO regulator powers the auxiliary devices.

The VRRTC voltage regulator is a programmable, LDO, linear voltage regulator supplying (1.5 V) the

embedded RTC (32.768-kHz oscillator) and dedicated I/Os of the digital host counterpart. The VRRTC

regulator is also the supply voltage of the power-management digital state-machine. The VRRTC regulator

is supplied from the UPR line, switched on by the main battery. The VRRTC output is present as long as a

valid energy source is present. The VRRTC line is supplied by an LDO when VBAT > 2.7 V, and a clamp

circuit when VBAT < 2.7 V.

The VINTDIG LDO regulator supplies the TPS65921 digital blocks.

To supply the TPS65921 analog blocks, there are two LDOs: VINTANA1 (1.5 V) and VINTANA2 (2.75

V/2.5 V). The 2.5-V setting is selected when the battery voltage falls below 3.0 V.

The VUSB3V1 internal LDO regulator powers the USB PHY, charger detection, and OTG of the USB

subchip inside the TPS65921 device.

It can take its power from two possible sources:

•

VBAT.USB (only for high battery voltages)

•

VBUS (only in low-power mode)

See Charge-pump section for more details.

The USB standard requires data lines to be biased with pullups biased from a > 3.0 V supply, USB PHY

cannot directly operate from VBAT.USB for battery voltages lower than 3.3 V.

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