TPS65921 datasheet(56/70 Pages) TI2

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TPS65921

SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014

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USB charger detection status bit definition:

•

USBVBUS_PRES:

Detect

presence

valid

VBUS.

Comparator

output

debounced

for

DEBVBUS_TIME (minimum 10 ms) on CKCHG and generates a USB_P signal. USB_P is computed

only if a battery presence is detected.

•

USBCHRG_PRES: Detect presence of USB charger on DP/DM. The feature is enabled through the

USB_DET_EN

signal,

then

USBPHY

performs

checks

DP/DM

and

return

status

USB_DET_RESULT:

–

1 : USB 500-mA charger is detected.

–

0 : USB 100-mA charger is detected.

•

USB_DET_STATUS: 500-mA/100-mA USB charger detect presence comparator output is debounced

during DEBUSBCHG_TIME (minimum 20 ms) on CKCHG, debounced signal is USB_DET_RESULT

(set to 1 in case of 500-mA charger)

•

Two signals are the result of the charger detection state machine:

–

USB100_P: Valid 100-mA charger (VBUS supplier) is detected.

–

USB500_P: Valid 500-mA charger (USB charger) is detected.

5.6.1

USB Battery Charger FSM

The FSM uses the control signals CHGDCTRL[6:0] described below to control and observe battery

charger detection.

When the SW_CONTROL bit is set to 1, the current context of the FSM and the state of charger detection

latched

POWER_CONTROL

bits

HWDETECT,

DP_VSRC_EN,

VDAT_DET,

and

DET_COMP, after which FSM control signals CHGDCTRL[6:0] are ignored, and charger detection

hardware and the CHGR_DET pin are controlled by the software.

The CHGD_IDP_SRC_EN bit is not latched when the SW_CONTROL bit is set (for example, if the FSM is

performing data-contact detection at the time the SW_CONTROL is set to 1, the CHGD_IDP_SRC_EN bit

is unchanged — its default value is 0).

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