TPS65921 datasheet(57/70 Pages) TI2

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TPS65921

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SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014

5.6.2

FSM Control Signals

Table 5-1. USB Charger Detect FSM I/O Control Signals

CONTROL SIGNAL

DESCRIPTION

TYPE

Bit(6)

USB500_P

500-mA USB charging can be enabled

Input

Bit(5)

USB100_P

100-mA USB charging can be enabled

Input

Bit(4)

CHGD_DET_EN

Enable charger detection (used to enable

Output

CHGD IBIAS block)

Bit(3)

CHGD_IDP_SRC_EN

Enable IDP_SRC and RDM_DWN

Output

Bit(2)

CHGD_VDP_SRC_EN

Enable VDP_SRC buffer, IDM_SINK, and

Output

VDAT_REF_DM comp

Bit(1)

CHGD_SERX_EN

Enable SERX comparators on DP and DM

Output

Bit(0)

Reserved

Output

Table 5-1 shows control signals used to control the charger detection analog block from the FSM. The bit

number in the left-handed column indicates control bit position used in the charger detection state-

machine. Both SERX comparator outputs (CHGD_SERX_DP, CHGD_SERX_DM) are available for

Example:

State: DCD_INIT

Control: CHGDCTRL[6:0] = 011_1010

Bit(6): USB500_P = 0

Bit(5): USB100_P = 1

Bit(4): CHGD_DET_EN = 1

Bit(3): CHGD_IDP_SRC_EN = 1

Bit(2): CHGD_VDP_SRC_EN = 0

Bit(1): CHGD_SERX_EN = 1

Bit(0): Reserved = 0

5.7

MADC

The Monitoring Analog-to-Digital Convertor (MADC) enables the host processors to monitor analog signals

using Analog-to-Digital Conversion (ADC). After the conversion is complete, the host processor reads the

results of the conversion through the inter-integrated circuit (I2C) interface.

The MADC has the following features:

•

10-bit ADC

•

External input (ADCIN0)

•

Internal inputs (VBUS and battery voltage)

•

MADC resource shared among multiple users, including system host processors and the internal USB

•

Four ways of starting analog-to-digital (ADC) conversion

•

Quarter-bit accuracy if the averaging function is used for modem-initiated real-time (RT) conversion

requests

•

Management of potential concurrent conversion requests and priority between different resource users

•

Interrupt signal to the primary interrupt handler (PIH) module at the end-of-sequence of conversions

•

Averaging feature to sample the input channel on four consecutive conversion cycles instead of once,

and to provide the average value of four conversions

Detailed Description

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