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TPS65921 Datasheet(PDF) 10 Page - Texas Instruments

Part # TPS65921
Description  TPS65921 Power Management and USB Single Chip
PDF  70 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TPS65921 Datasheet(HTML) 10 Page - Texas Instruments

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TPS65921
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
www.ti.com
4
Specifications
4.1
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Main battery supply
0.0
5.0
V
voltage(2)
Where supply represents the voltage
Voltage on any input(3)
applied to the power supply pin
–0.3
1.0 × Supply + 0.3
V
associated with the input(4)
VBUS input
–0.3
7
V
Operating ambient
–40
85
°C
temperature (TA)
Operating junction
Absolute maximum rating
–40
125
°C
temperature (TJ)
Operating junction
For parametric compliance
–40
150
°C
temperature (TJ)
Ambient temperature for
With maximum 125°C as junction
–40
85
°C
parametric compliance
temperature (TJ)
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
(2)
The product will have negligible reliability impact if voltage spikes of 5.2 V occur for a total (cumulative over lifetime) duration of 10
milliseconds.
(3)
Excepts VBAT input pads and VBUS pad.
(4)
Supply equals the reference level of each pin.
4.2
Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–55
125
°C
Human Body Model (HBM), per ANSI/ESDA/JEDEC
–1
1
kV
JS001(1)
Electrostatic discharge (ESD)
VESD
performance:
Charged Device Model (CDM),
All pins
–250
250
V
per JESD22-C101(2)
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4.3
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
Power and USB Path
VBAT/VBAT.USB main battery supply voltage and
2.7
3.6
4.5
V
VBUS
0
7
V
HFCLKIN Input Clock
Frequency 1/tC(HFCLKIN)
19.2, 26 or 38.4
MHz
0.55 ×
Pulse duration, HFCLKIN low or high (BP)
0.45 × tC(HFCLKIN)
ns
tC(HFCLKIN)
HFCLKIN stability
–150
150
ppm
Rise time of HFCLKIN (BP)
0
5
ns
Fall time of HFCLKIN (BP)
0
5
ns
LP/HP (sine wave)
0.3
0.7
1.45
Vpp
Input dynamic range
BP/PD (square wave)
0
1.85(1)
Vpp
Harmonic content of input signal (with 0.7-VPP amplitude): Second
–25
dBc
component - LP/HP (sine wave)
VIH voltage input
BP (square mode)
0.65 × IO.1P8
V
high(1)
(1)
Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface (IO.1P8V).
10
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
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