TPS65921 datasheet(49/70 Pages) TI2

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VBAT

DEVOFF (register)

NRESPWRON

REGEN

32K

OUT

CLK

DCDCs

LDOs

SYSEN

HFCLKOUT

CLKEN

NEXT_Startup_event

18 s

1,2 ms

18 s

3.42 ms before detection of starting event

126 s

SWCS048-021

1,2 ms

TPS65921

www.ti.com

SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014

5.5.5.3.1 Switch-Off Sequence In Master Modes

Figure 5-10 describes the timing and control that occur during the switch-off sequence in master modes.

NOTE: All of the above timings are the typical values with the default setup (depending on the resynchronization between

power domains, state machinery priority, and so forth).

Figure 5-10. Switch-Off Sequence in Master Modes

In case the value of the HF clock is different from 19.2 MHz (with HFCLK_FREQ bit field values set

accordingly

inside

the

CFG_BOOT

then

the

delay

between

DEVOFF

and

NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided by 2 (meaning around 9

μs). This is due to

the internal frequency used by POWER STM switching from 3 MHz to 1.5 MHz in case the value of the

HF clock is 19.2 MHz.

The DEVOFF event is the PWRON falling edge in slave mode and the DEVOFF internal register write in

master mode.

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