CC113LRGP datasheet(26/87 Pages) TI2

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CC113L

SWRS108B – MAY 2011 – REVISED JUNE 2014

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5.9

Demodulator, Symbol Synchronizer, and Data Decision

CC113L contains an advanced and highly configurable demodulator. Channel filtering and frequency

offset compensation is performed digitally. To generate the RSSI level (see Section 5.12.2 for more

information), the signal level in the channel is estimated. Data filtering is also included for enhanced

performance.

5.9.1

Frequency Offset Compensation

The CC113L has a very fine frequency resolution (see Section 4.8). This feature can be used to

compensate for frequency offset and drift.

When using 2-FSK, GFSK, or 4-FSK modulation, the demodulator will compensate for the offset between

the transmitter and receiver frequency within certain limits, by estimating the center of the received data.

The frequency offset compensation configuration is controlled from the FOCCFG register. By

compensating for a large frequency offset between the transmitter and the receiver, the sensitivity can be

improved, see DN005 SWRA122.

The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the

FOCCFG.FOC_LIMIT configuration register.

If the FOCCFG.FOC_BS_CS_GATE bit is set, the offset compensator will freeze until carrier sense

asserts. This may be useful when the radio is in RX for long periods with no traffic, since the algorithm

may drift to the boundaries when trying to track noise.

The tracking loop has two gain factors, which affects the settling time and noise sensitivity of the

algorithm.

FOCCFG.FOC_PRE_K

sets

the

gain

before

the

sync

word

detected,

and

FOCCFG.FOC_POST_K selects the gain after the sync word has been found.

NOTE

Frequency offset compensation is not supported for OOK modulation.

The estimated frequency offset value is available in the FREQEST status register. This can be used for

permanent frequency offset compensation. By writing the value from FREQEST into FSCTRL0.FREQOFF,

the frequency synthesizer will automatically be adjusted according to the estimated frequency offset. More

details regarding this permanent frequency compensation algorithm can be found in DN015 SWRA159.

5.9.2

Bit Synchronization

The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires

that the expected data rate is programmed as described in Section 5.7. Re-synchronization is performed

continuously to adjust for error in the incoming symbol rate.

5.9.3

Byte Synchronization

Byte synchronization is achieved by a continuous sync word search. The sync word is a 16 bit

configurable field (can be repeated to get a 32 bit) that must be inserted at the start of the packet by the

transmitter (for example the CC115L, CC110L, or CC1101). The MSB in the sync word must be

transmitted first. The demodulator uses this field to find the byte boundaries in the stream of bits. The sync

word will also function as a system identifier, since only packets with the correct predefined sync word will

be received if the sync word detection in RX is enabled in register MDMCFG2 (see Section 5.12.1). The

sync word detector correlates against the user-configured 16 or 32 bit sync word. The correlation

threshold can be set to 15/16, 16/16, or 30/32 bits match. The sync word can be further qualified using the

preamble quality indicator mechanism described below and/or a carrier sense condition. The sync word is

configured through the SYNC1 and SYNC0 registers.

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