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CC113LRGP Datasheet(PDF) 53 Page - Texas Instruments

Part # CC113LRGP
Description  CC113L Value Line Receiver
PDF  87 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

CC113LRGP Datasheet(HTML) 53 Page - Texas Instruments

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CC113L
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SWRS108B – MAY 2011 – REVISED JUNE 2014
Table 5-19. SPI Address Space (continued)
Write
Read
Single Byte
Burst
Single Byte
Burst
+0x00
+0x40
+0x80
+0xC0
0x30
SRES
SRES
PARTNUM
0x31
Reserved
Reserved
VERSION
0x32
SXOFF
SXOFF
FREQEST
0x33
SCAL
SCAL
CRC_REG
0x34
SRX
SRX
RSSI
0x35
Reserved
Reserved
MARCSTATE
0x36
SIDLE
SIDLE
Reserved
0x37
Reserved
Reserved
Reserved
0x38
Reserved
Reserved
PKTSTATUS
0x39
SPWD
SPWD
Reserved
0x3A
SFRX
SFRX
Reserved
0x3B
Reserved
Reserved
RXBYTES
0x3C
Reserved
Reserved
Reserved
0x3D
SNOP
SNOP
Reserved
0x3E
Reserved
Reserved
Reserved
0x3F
Reserved
RX FIFO
RX FIFO
5.21.1 Configuration Register Details - Registers with preserved values in SLEEP state
Table 5-20. 0x00: IOCFG2 - GDO2 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
R0
Not used
6
GDO2_INV
0
R/W
Invert output, that is, select active low (1) / high (0)
5:0
GDO2_CFG[5:0]
41 (101001)
R/W
Default is CHP_RDYn (see Table 5-15).
Table 5-21. 0x01: IOCFG1 - GDO1 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
Set high (1) or low (0) output drive strength on the GDO
7
GDO_DS
0
R/W
pins.
6
GDO1_INV
0
R/W
Invert output, that is, select active low (1) / high (0)
5:0
GDO1_CFG[5:0]
46 (101110)
R/W
Default is 3-state (see Table 5-15).
Table 5-22. 0x02: IOCFG0 - GDO0 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
0
R/W
Use setting from SmartRF Studio
6
GDO0_INV
0
R/W
Invert output, that is, select active low (1) / high (0)
Default is CLK_XOSC/192 (see Table 5-15).
5:0
GDO0_CFG[5:0]
63 (0x3F)
R/W
It is recommended to disable the clock output in
initialization, in order to optimize RF performance.
Copyright © 2011–2014, Texas Instruments Incorporated
Detailed Description
53
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Product Folder Links: CC113L



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