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CC113LRGP Datasheet(PDF) 12 Page - Texas Instruments |
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CC113LRGP Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 87 page  CC113L SWRS108B – MAY 2011 – REVISED JUNE 2014 www.ti.com 4.8 Frequency Synthesizer Characteristics TA = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results are obtained using SWRR046 and SWRR045. Min figures are given using a 27-MHz crystal. Typ and max figures are given using a 26-MHz crystal. Parameter Min Typ Max Unit Condition Programmed frequency 26- to 27-MHz crystal. The resolution (in Hz) is 397 FXOSC/2 16 412 Hz resolution equal for all frequency bands Given by crystal used. Required accuracy (including temperature and aging) depends on Synthesizer frequency tolerance ±40 ppm frequency band and channel bandwidth / spacing RF carrier phase noise –92 dBc/Hz at 50 kHz offset from carrier RF carrier phase noise –92 dBc/Hz at 100 kHz offset from carrier RF carrier phase noise –92 dBc/Hz at 200 kHz offset from carrier RF carrier phase noise –98 dBc/Hz at 500 kHz offset from carrier RF carrier phase noise –107 dBc/Hz at 1 MHz offset from carrier RF carrier phase noise –113 dBc/Hz at 2 MHz offset from carrier RF carrier phase noise –119 dBc/Hz at 5 MHz offset from carrier RF carrier phase noise –129 dBc/Hz at 10 MHz offset from carrier Time from leaving the IDLE state until arriving in PLL turn-on or hop time 72 75 75 µs the RX state, when not performing calibration. (See Table 5-12) Crystal oscillator running. PLL calibration time Calibration can be initiated manually or 685 712 724 µs (See Table 5-13) automatically before entering or after leaving RX 4.9 DC Characteristics TA = 25°C if nothing else stated. Digital Inputs/Outputs Min Max Unit Condition Logic "0" input voltage 0 0.7 V Logic "1" input voltage VDD – 0.7 VDD V Logic "0" output voltage 0 0.5 V For up to 4 mA output current Logic "1" output voltage VDD – 0.3 VDD V For up to 4 mA output current Logic "0" input current N/A –50 nA Input equals 0 V Logic "1" input current N/A 50 nA Input equals VDD 4.10 Power-On Reset For proper Power-On-Reset functionality the power supply should comply with the requirements in Section 4.10. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 5.13.1, Power-On Start-Up Sequence, for further details. Parameter Min Typ Max Unit Condition Power-up ramp-up time 5 ms From 0 V until reaching 1.8 V Power off time 1 ms Minimum time between power-on and power-off 4.11 Thermal Characteristics (1) NAME DESCRIPTION QFN (°C/W) RθJA Junction-to-ambient thermal resistance 47 RθJC(top) Junction-to-case (top) thermal resistance 45 RθJB Junction-to-board thermal resistance 13.6 RθJC(bot) Junction-to-case (bottom) thermal resistance 5.12 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 12 Specifications Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC113L |
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