STA333BW datasheet(58/64 Pages) STMICROELECTRONICS

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STA333BW

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6.15

Fault detect recovery constant registers (0x2B to 0x2C)

FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the

TRISTATE output is immediately asserted low and held low for the time period specified by

this constant. A constant value of 0x0001 in this register is ~.083 ms. The default value of

0x000C specifies ~.1 mS.

6.16

Device status register (0x2D)

This read-only register provides fault and thermal-warning status information from the power

control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault

or warning detected on power bridge. The PLLUL=’1’ means that the PLL is not locked.

PLLUL: 0 = PLL locked, 1= PLL not locked.

FAULT: 0 = fault detected on power bridge, 1 = normal operation

UVFAULT: 0 = VCC1, VCC2 internally detected < under-voltage threshold.

OVFAULT: 0 = VCC1, VCC2 internally detected > over-voltage threshold.

OCFAULT: 0 = over-current fault detected

OCWARN: 0 = over-current warning.

TFAULT: 0 = thermal fault, junction temperature over-limit detection.

TWARN: 0 = thermal warning, junction temperature is close to the fault condition.

DCC7

DCC6

DCC5

DCC4

DCC3

DCC2

DCC1

DCC0

011

FDRC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

000

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

000

PLLUL

FAULT

UVFAULT

OVFAULT

OCFAULT

OCWARN

TFAULT

TWARN

STA333BW Datasheet(PDF) 58 Page - STMicroelectronics

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