| Electronic Components Datasheet Search |
|
STA333BW Datasheet(PDF) 15 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STA333BW Datasheet(HTML) 15 Page - STMicroelectronics |
|
15 / 64 page ![]() STA333BW Electrical specifications 15/64 3.5 Power-on sequence Figure 3. Power-on sequence Referring to Figure 3 above: TR = mimimum time between XTI master clock stable and reset removal: 1 ms, TC = minimum time between reset removal and I2C program sequence start: 1 ms. Note: Clock stable means: fmax - fmin < 1 MHz. Note: VCC > VDD_DIG must be guaranteed at all times. 3.6 Testing 3.6.1 Functional pin status Don’t care Don’t care CMD0 CMD1 CMD2 VCC VDD_DIG XTI Reset I2C PWDN TR TC Don’t care Don’t care CMD0 CMD1 CMD2 VCC VDD_DIG XTI Reset I2C PWDN TR TC Table 7. Functional pin status Pin name Number Logic value IC status PWRDN 23 0 Low-power mode PWRDN 23 1 Normal operation TWARN 20 0 Temperature warning from external power stage TWARN 20 1 Normal operation EAPD 19 0 Low-power operation for power stage. All internal regulators are switched off EAPD 19 1 Normal operation |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |