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STA333BW Datasheet(PDF) 33 Page - STMicroelectronics |
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STA333BW Datasheet(HTML) 33 Page - STMicroelectronics |
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33 / 64 page ![]() STA333BW Register description 33/64 6.6 Configuration register F (0x05) 6.6.1 Output configuration Note: To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs. D7 D6 D5 D4 D3 D2 D1 D0 EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0 01 0 1 1 1 0 0 Bit R/W RST Name Description 0 R/W 0 OCFG0 Selects the output configuration 1 R/W 0 OCFG1 Table 15. Output configuration engine selection OCFG[1:0] Output configuration Config PIN 00 2-channel (full-bridge) power, 2 channel data-out: 1A/1B → 1A/1B 2A/2B → 2A/2B Line out1 → 3A/3B Line out2 → 4A/4B Line out configuration determined by LOC register 0 01 2(half-bridge).1(full-bridge) on-board power: 1A → 1A binary 0 ° 2A → 1B binary 90° 3A/3B → 2A/2B binary 45° 1A/B → 3A/B binary 0° 2A/B → 4A/B binary 90° 0 10 2-channel (full-bridge) power, 1 channel DDX: 1A/1B → 1A/1B 2A/2B → 2A/2B 3A/3B → 3A/3B EAPDEXT and TWARNEXT Active 0 11 1-channel mono-parallel: 3A → 1A/1B w/ C3BO 45° 3B → 2A/2B w/ C3BO 45° 1A/1B → 3A/3B 2A/2B → 4A/4B 1 |
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