STA333BW datasheet(39/64 Pages) STMICROELECTRONICS

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6.6.6

IC power down

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

to power down the power-stage, then the master clock to all internal hardware expect the

I2C block is gated. This places the IC in a very low power consumption state.

6.6.7

External amplifier power down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed on a low-power state (disabled). This

6.7

Volume control registers (0x06 to 0x0A)

6.7.1

Mute/line output configuration register

Line output is only active when OCFG = 00. In this case LOC determines the line output

configuration. The source of the line output is always the channel 1 and 2 inputs.

6.7.2

Master volume register

Bit

R/W

RST

Name

Description

7R/W

PWDN

0: IC power down low-power condition

1: IC normal operation

Bit

R/W

RST

Name

Description

R/W

EAPD

0: external power stage power down active

1: normal operation

LOC1

LOC0

C3M

C2M

C1M

MMUTE

LOC[1:0]

Line output configuration

Line output fixed, no volume, no EQ

Line output variable, CH3 volume effects line output, no EQ

Line output variable with EQ, CH3 volume effects line output

MV7

MV6

MV5

MV4

MV3

MV2

MV1

MV0

111

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