STA333BW datasheet(28/64 Pages) STMICROELECTRONICS

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STA333BW

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6.3

Configuration register C (0x02)

6.3.1

DDX power output mode

The DDX power output mode selects how the DDX output timing is configured.

Different power devices use different output modes.

6.3.2

DDX compensating pulse size register

Table 6:

OCRB

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

101

Bit

R/W

RST

Name

Description

0R/W

OM0

Selects configuration of DDX output.

1R/W

OM1

Table 13.

Output modes

OM[1,0]

Output stage / mode

Drop Compensation

Discrete Output Stage, Tapered Compensation

Full Power Mode

Variable Drop Compensation (CSZx bits)

Bit

R/W

RST

Name

Description

2R/W

CSZ0

When OM[1,0] = 11, this register determines the

size of the DDX compensating pulse from 0 clock

ticks to 15 clock periods.

3R/W

CSZ1

4R/W

CSZ2

5R/W

CSZ3

Table 14.

Compensating pulse size

CSZ[3:0]

Compensating Pulse Size

0000

0 ns (0 tick) compensating pulse size

0001

20 ns (1 tick) clock period compensating pulse size

……

1111

300 ns (15 tick) clock period compensating pulse size

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