STA333BW datasheet(38/64 Pages) STMICROELECTRONICS

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STA333BW

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Figure 17.

2.1 channels (OCFG=’10’) PWM slots.

6.6.2

Invalid input detect mute enable

Setting the IDE bit enables this function, which looks at the input I2S data and will

automatically mute if the signals are perceived as invalid.

6.6.3

Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

6.6.4

LRCK double trigger protection

Actively prevents double trigger of LRCLK.

6.6.5

Auto EAPD on clock loss

When active, issues a power device power down signal (EAPD) on clock loss detection.

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

Bit

R/W

RST

Name

Description

2R/W

IDE

Setting of 1 enables the automatic invalid input

detect mute

Bit

R/W

RST

Name

Description

R/W

BCLE

Binary output mode clock loss detection enable

Bit

R/W

RST

Name

Description

R/W

LDTE

LRCLK double trigger protection enable

Bit

R/W

RST

Name

Description

R/W

ECLE

Auto EAPD on clock loss

STA333BW Datasheet(PDF) 38 Page - STMicroelectronics

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