C8051F310 datasheet(210/228 Pages) SILABS

210 / 228 page

C8051F310/1/2/3/4/5/6/7

210

Rev. 1.7

18.2.5. 8-Bit Pulse Width Modulator Mode

Each module can be used independently to generate a pulse width modulated (PWM) output on its associ-

ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The

duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.

When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the

output on the CEXn pin will be set. When the count value in PCA0L overflows, the CEXn output will be

reset (see Figure 18.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00,

PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare high byte

(PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register

enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 18.2.

Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/

Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit

to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.

Using Equation 18.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is

0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.

Figure 18.8. PCA 8-Bit PWM Mode Diagram

DutyCycle

256

PCA0CPHn

–

()

256

---------------------------------------------------

Equation 18.2. 8-Bit PWM Duty Cycle

8-bit

Comparator

PCA0L

PCA0CPLn

PCA0CPHn

CEXn

Crossbar

Port I/O

Enable

Overflow

PCA Timebase

00 x 0

SET

CLR

match

PCA0CPMn

ENB

Write to

PCA0CPLn

Write to

PCA0CPHn

Reset

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