C8051F310 datasheet(212/228 Pages) SILABS

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C8051F310/1/2/3/4/5/6/7

212

Rev. 1.7

18.3. Watchdog Timer Mode

A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used

to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified

limit. The WDT can be configured and enabled/disabled as needed by software.

With the WDTE bit set in the PCA0MD register, Module 4 operates as a watchdog timer (WDT). The Mod-

ule 4 high byte is compared to the PCA counter high byte; the Module 4 low byte holds the offset to be

used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some

PCA registers are restricted while the Watchdog Timer is enabled.

18.3.1. Watchdog Timer Operation

While the WDT is enabled:

•

PCA counter is forced on.

•

Writes to PCA0L and PCA0H are not allowed.

•

PCA clock source bits (CPS2-CPS0) are frozen.

•

PCA Idle control bit (CIDL) is frozen.

•

Module 4 is forced into software timer mode.

•

Writes to the Module 4 mode register (PCA0CPM4) are disabled.

While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run

until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user

software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while the

WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write

of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is loaded

into PCA0CPH4 (See Figure 18.10).

Figure 18.10. PCA Module 4 with Watchdog Timer Enabled

PCA0H

Enable

PCA0L Overflow

Reset

PCA0CPL4

8-bit Adder

PCA0CPH4

Adder

Enable

PCA0MD

Match

Write to

PCA0CPH4

8-bit

Comparator

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