Data Sheet

AD4002/AD4006/AD4010

Rev. A | Page 31 of 39

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is typically used when a single AD4002/AD4006/

AD4010 device is connected to an SPI-compatible digital host.

The connection diagram is shown in Figure 53, and the

corresponding timing diagram is shown in Figure 54.

Turbo mode must be disabled to use this mode. To disable turbo

mode, set the turbo mode enable field in the configuration

register to 0 (see Table 12). Turbo mode is disabled by default.

When performing conversions in this mode, SDI must be held

high. SDI can be connected to VIO if register reading and writing

is not required. A rising edge on CNV initiates a conversion and

forces SDO to high impedance. After a conversion is initiated, it

continues until completion irrespective of the state of CNV. This

feature can be useful, when bringing CNV low to select other

SPI devices, such as analog multiplexers. However, CNV must

be returned high before the minimum conversion time (tCONV)

elapses and then held high for the maximum possible

conversion time to avoid the generation of the busy signal

indicator. When the conversion is complete, the AD4002/

AD4006/AD4010 enter the acquisition phase and power-down.

There must not be any digital activity on SCK during the

conversion.

When CNV goes low, the MSB is output onto SDO. The remaining

data bits are clocked out on SDO by subsequent SCK falling edges.

The data is valid on both SCK edges. Although the rising edge

can capture the data, a digital host using the SCK falling edge

allows a faster reading rate, provided it has an acceptable hold

time, as dictated by tHSDO (see Table 2). If the status bits are not

enabled, SDO returns to high impedance after the 18th SCK

falling edge. If the status bits are enabled, they are shifted out on

SDO on the 19th through the 24th SCK falling edges (see the

Status Bits section). SDO returns to high impedance after the

final SCK falling edge, or when CNV goes high (whichever

occurs first).

AD4002/

AD4006/

AD4010

SDI1

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

1SDI MUST BE CONNECTED TO THE DIGITAL HOST DATA OUT

TO WRITE TO THE CONFIGURATION REGISTER

Figure 53. CS Mode, 3-Wire Without Busy Indicator Connection Diagram

SDO

D17

D16

D15

D1

D0

tDIS

SCK

12

3

16

17

18

tSCK

tSCKL

tSCKH

HSDO

tDSDO

CNV

CONVERSION

ACQUISITION

tCYC

ACQUISITION

SDI = 1

tCNVH

tACQ

tEN

tQUIET2

tCONV

Figure 54. CS Mode, 3-Wire Without the Busy Indicator Serial Interface Timing Diagram (Status Bits Not Shown)