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AD4002 Datasheet(PDF) 28 Page - Analog Devices |
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AD4002 Datasheet(HTML) 28 Page - Analog Devices |
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28 / 39 page ![]() AD4002/AD4006/AD4010 Data Sheet Rev. A | Page 28 of 39 tCYC tSCK tSCKL tSCKH tSCNVSCK tSSDISCK tHSDISCK tCNVH1 EN tHSDO tDSDO tDIS tHCNVSCK tQUIET22 1THE CNV HIGH TIME MUST FOLLOW THE tCONV SPECIFICATION TO GENERATE A VALID CONVERSION RESULT 2THE SCK FALLING EDGE TO CNV RISING EDGE DELAY MUST FOLLOW THE tQUIET2 SPECIFICATION TO ENSURE SPECIFIED PERFORMANCE SDO D0 D1 D2 D3 D4 D5 D6 D7 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 CONVERSION RESULT ON D17 TO D0 SDI 01 01 R/W WEN B0 B1 B2 B3 B4 B5 B6 B7 00 1 1 (0) (0) 8-BIT REGISTER ACCESS COMMAND REGISTER DATA ON B7 TO B0 SCK 12 3 4 5 67 8 9 10 11 1213141516 1718 CNV Figure 48. Register Write Timing Diagram tCYC tSCK tSCKL tSCKH tSCNVSCK SDIA SDOA/SDIB SDOB CNV SCK tDIS tCNVH 0 0 COMMAND (0x14) 0 0 COMMAND (0x14) 0 0 COMMAND (0x14) 1 24 DATA (0xAB) DATA (0xAB) Figure 49. Register Write Timing Diagram, Daisy-Chain Mode |
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