AD4002 datasheet(24/39 Pages) AD

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AD4002/AD4006/AD4010

Data Sheet

Rev. A | Page 24 of 39

Additionally, the AD4002/AD4006/AD4010 can be driven with

a much higher source impedance than traditional SARs, which

means the resistor in the RC filter can have a value 10 times larger

than previous SAR designs and with high-Z mode enabled can

tolerate even greater impedance. Figure 26 shows the THD

performance for various source impedances with high-Z

mode disabled and enabled.

Figure 45 and Figure 46 show the AD4002 SNR and THD

performance using the ADA4077-1 (supply current per

amplifier (ISY) = 400 μA), and ADA4610-1 (ISY = 1.50 mA)

precision amplifiers when driving the AD4002 at full throughput

(2 MSPS) for high-Z mode both enabled and disabled with various

RC filter values. These amplifiers achieve 93.2 dB and 90.7 dB

typical SNR and −111 dB and −105 dB typical THD with high-Z

enabled for a 2.27 MHz RC bandwidth, respectively. THD is

approximately 10 dB better with high-Z mode enabled, even for

large R values. SNR maintains close to 88 dB even with a low

RC filter cutoff. The ADA4077-1 and ADA4610-1 data sheets of

the selected precision amplifiers (see Figure 45 and Figure 46)

show that their own noise and distortion performance dominates

the SNR and THD specification at a certain input frequency.

When high-Z mode is enabled, the ADC consumes approximately

2 mW per MSPS extra power. However, this additional power is

still significantly lower than using dedicated ADC drivers like

the ADA4807-1.

260.48kHz

1.3kΩ 470pF

5.89MHz

150Ω 180pF

4.42MHz

200Ω 180pF

2.27MHz

390Ω 180pF

1.3MHz

680Ω 180pF

497.98kHz

680Ω 470pF

RC FILTER BANDWIDTH (Hz)

RESISTOR (Ω), CAPACITOR (pF)

ADA4077-1 HIGH-Z ENABLED

ADA4077-1 HIGH-Z DISABLED

ADA4610-1 HIGH-Z ENABLED

ADA4610-1 HIGH-Z DISABLED

Figure 45. SNR vs. RC Filter Bandwidths for Various Precision ADC Drivers,

fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V,

VIO = 3.3 V, VREF = 5 V, TA = 25°C

–70

–120

–110

–100

–90

–80

–75

–115

–105

–95

–85

260.48kHz

1.3kΩ 470pF

5.89MHz

150Ω 180pF

4.42MHz

200Ω 180pF

2.27MHz

390Ω 180pF

1.3MHz

680Ω 180pF

497.98kHz

680Ω 470pF

RC FILTER BANDWIDTH (Hz)

RESISTOR (Ω), CAPACITOR (pF)

ADA4077-1 HIGH-Z ENABLED

ADA4077-1 HIGH-Z DISABLED

ADA4610-1 HIGH-Z ENABLED

ADA4610-1 HIGH-Z DISABLED

Figure 46. THD vs. RC Bandwidths for Various Precision ADC Drivers,

fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V,

VIO = 3.3 V, VREF = 5 V, TA = 25°C

Long Acquisition Phase

The AD4002/AD4006/AD4010 also feature a very fast conversion

time of 290 ns, which results in a long acquisition phase. The

acquisition is further extended by a key feature of the AD4002/

AD4006/AD4010: the ADC returns to the acquisition phase

typically 100 ns before the end of the conversion. This feature

provides an even longer time for the ADC to acquire the new

input voltage. A longer acquisition phase reduces the settling

requirement on the driving amplifier, and a lower power and lower

bandwidth amplifier can be chosen. The longer acquisition

phase means that a lower RC filter (represented by R and C in

Figure 39 and Figure 40) cutoff can be used, which means a

noisier amplifier can also be tolerated. A larger value of R can

be used in the RC filter with a corresponding smaller value of C,

reducing amplifier stability concerns without affecting distortion

performance significantly. A larger value of R also results in

reduced dynamic power dissipation in the amplifier.

See Table 10 for details on setting the RC filter bandwidth and

choosing a suitable amplifier.

VOLTAGE REFERENCE INPUT

A 10 μF (X7R, 0805 size) ceramic chip capacitor is appropriate

for the optimum performance of the reference input.

For higher performance and lower drift, use a reference such

as the ADR4550. Using a low power reference such as the

ADR3450 can result in a decrease in the noise performance. It is

recommended to use a reference buffer, such as the ADA4807-1,

between the reference and the ADC reference input. It is important

to consider the optimum capacitance necessary to keep the

reference buffer stable as well as to meet the minimum ADC

requirement stated previously in this section (that is, a 10 μF

ceramic chip capacitor, CREF).

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