AD4002 datasheet(33/39 Pages) AD

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Data Sheet

AD4002/AD4006/AD4010

Rev. A | Page 33 of 39

CS MODE, 4-WIRE TURBO MODE

This mode is typically used when a single AD4002/AD4006/

AD4010 device is connected to an SPI-compatible digital host.

Turbo mode allows lower SCK frequencies by increasing the time

that the ADC conversion result can be clocked out. The AD4002

can achieve a throughput rate of 2 MSPS only when turbo mode is

enabled and using a minimum SCK frequency of 75 MHz (see the

Serial Clock Frequency Requirements section). The connection

diagram is shown in Figure 57, and the corresponding timing

diagram is shown in Figure 58.

To enable turbo mode, set the turbo mode enable field in the

configuration register to 1 (see Table 12). This mode replaces

the 4-wire with busy indicator mode when turbo mode is enabled.

The digital host must be able to write data over SDI to perform

section). When turbo mode is enabled, the conversion result read

on SDO corresponds to the result of the previous conversion.

A rising edge on CNV initiates a conversion and forces SDO to

high impedance. CNV must be held high throughout the

conversion and data readback phase. When performing

conversions in this mode, SDI must be high during the CNV

rising edge. The user must wait tQUIET1 time after the CNV rising

edge before bringing SDI low to clock out the previous conversion

result. When the conversion is complete (after tCONV), the AD4002/

AD4006/AD4010 enter the acquisition phase and power-down.

SDI is analogous to a chip select input, and bringing SDI low

outputs the MSB of the conversion result on SDO. The remaining

data bits are clocked out on SDO by subsequent SCK falling

edges. The data is valid on both SCK edges. Although the rising

edge can capture the data, a digital host using the SCK falling

edge allows a faster reading rate, provided it has an acceptable

hold time, as dictated by tHSDO (see Table 2). The conversion result

is clocked out on SDO on the first 18 SCK falling edges. If the

status bits are enabled, they are shifted out on SDO on the 19th

through the 24th SCK falling edges (see the Status Bits section).

SDO returns to high impedance after the final SCK falling edge,

or when CNV goes high (whichever occurs first). The user must

also provide a delay of tQUIET2 between the final SCK falling edge

and the next CNV rising edge to ensure specified performance.

AD4002/

AD4006/

AD4010

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

DATA OUT

Figure 57. CS Mode, 4-Wire Turbo Mode Connection Diagram

ACQUISITION

SDO

SCK

ACQUISITION

SDI

CNV

tSSDICNV

tHSDICNV

tCYC

tSCK

tSCKL

tEN

tHSDO

tDSDO

tDIS

tSCKH

D17

D16

D15

tQUIET1

tQUIET2

tACQ

CONVERSION

tCONV

Figure 58. CS Mode, 4-Wire Turbo Mode Timing Diagram (Status Bits Not Shown)

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