AD4002/AD4006/AD4010

Data Sheet

Rev. A | Page 26 of 39

The minimum SCK frequency required to access the conversion

result plus status bits when turbo mode is not enabled is calculated

with the following equation:

2

DS

SCK

CYC

CONV

EN

QUIET

NN

f

tt

t

t









Where tCONV corresponds to the conversion time and is

described in Table 2.

Table 12. AD4002/AD4006/AD4010 Configuration Register

Bits

Bit Name

Description

Reset

Access1

[7:5]

Reserved

Reserved memory.

0x0

R

4

Status bits enable

Enables status bits (see the Status Bits section).

0x0

R/W

0: disables status bits.

1: enables status bits.

3

Span compression enable

Enables span compression (see the

Input Span

Compression section).

0x0

R/W

0: disables span compression.

1: enables span compression.

2

High-Z mode enable

Enables high-Z mode (see the

High-Z Mode section).

0x0

R/W

0: disables high-Z mode.

1: enables high-Z mode.

1

Turbo mode enable

Enables turbo mode.

0x0

R/W

0: disables turbo mode.

1: enables turbo mode.

0

OV clamp flag

Indicates an overvoltage event triggered the input

overvoltage clamp circuit (see the

Input Overvoltage

Clamp Circuit section). This bit is sticky, and clears only

when read after the overvoltage event has ended.

0x1

R

0: indicates an overvoltage event has occurred.

1: indicates no overvoltage event has occurred.

1 R stands for read-only, and R/W stands for read/write. Read-only bits cannot be updated with a register write operation. Read/write bits can be updated with a register

write operation.

Table 13. SCK Frequency Requirements for Various Throughputs

CS MODE

Throughput

Minimum SCK Frequency (MHz)

3-Wire and 4-Wire Turbo Modes

2 MSPS (AD4002)

75 MHz

1 MSPS (AD4002/AD4006)

25 MHz

500 kSPS (AD4002/AD4006/AD4010)

11 MHz

100 kSPS (AD4002/AD4006/AD4010)

2 MHz

3-Wire and 4-Wire Turbo Modes with Six Status Bits1

2 MSPS (AD4002)

100 MHz

1 MSPS (AD4002/AD4006)

33 MHz

500 kSPS (AD4002/AD4006/AD4010)

14 MHz

100 kSPS (AD4002/AD4006/AD4010)

2.5 MHz

3-Wire and 4-Wire Modes

1.8 MSPS (AD4002)

93 MHz

1 MSPS (AD4002/AD4006)

30 MHz

500 kSPS (AD4002/AD4006/AD4010)

11 MHz

100 kSPS (AD4002/AD4006/AD4010)

2 MHz

3-Wire and 4-Wire Modes with Six Status Bits1

1.6 MSPS (AD4002)

91 MHz

1 MSPS (AD4002/AD4006)

38 MHz

500 kSPS (AD4002/AD4006/AD4010)

15 MHz

100 kSPS (AD4002/AD4006/AD4010)

2.5 MHz

1 It is not necessary to clock out all six status bits. The minimum required SCK frequency is reduced when clocking out fewer than six status bits. See the Serial Clock

Frequency Requirements and the Status Bits section sections.