AD4002 datasheet(1/39 Pages) AD

Part #	AD4002

Description	18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs

PDF	39 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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18-Bit, 2 MSPS/1 MSPS/500 kSPS,

Precision, Pseudo Differential, SAR ADCs

Data Sheet

AD4002/AD4006/AD4010

Rev. A

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FEATURES

Easy Drive

Greatly reduced input kickback

Input current reduced to 0.5 μA/MSPS

Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS

First conversion accurate, no latency or pipeline delay

Input span compression for single-supply operation

Fast conversion allows low SPI clock rates

Input overvoltage clamp protection sinks up to 50 mA

SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface

High performance

Pseudo differential analog input range

0 V to VREF with VREF from 2.4 V to 5.1 V

Throughput: 2 MSPS/1 MSPS/500 kSPS options

INL: ±3.2 LSB maximum

Guaranteed 18-bit, no missing codes

SNR: 95 dB at fIN = 1 kHz at VREF = 5 V

THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz

SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17)

Oversampled dynamic range

98 dB for OSR = 2

125 dB for OSR = 1024

Low power

Single 1.8 V supply operation with 1.71 V to 5.5 V logic

interface

2.5 mW at 500 kSPS (VDD only)

70 μW at 10 kSPS, 14 mW at 2 MSPS (total power)

10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP

Pin compatible with AD4003/AD4007/AD4011 family

Guaranteed operation: −40°C to +125°C

APPLICATIONS

Automated test equipment

Machine automation

Medical equipment

Battery-powered equipment

Precision data acquisition systems

Instrumentation and control systems

FUNCTIONAL BLOCK DIAGRAM

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD4002/

AD4006/

AD4010

18-BIT

SAR ADC

SERIAL

INTERFACE

VIO

REF

VDD

VREF

0

VREF/2

HIGH-Z

MODE

CLAMP

SPAN

COMPRESSION

TURBO

MODE

STATUS

BITS

2.4V TO 5.1V

1.8V

10µF

1.8V TO 5V

3-WIRE OR 4-WIRE

SPI INTERFACE

(DAISY CHAIN, CS)

Figure 1.

GENERAL DESCRIPTION

The AD4002/AD4006/AD4010 are high accuracy, high speed,

low power, 1

8-bit, Easy Drive, precision successive approximation

register (SAR) analog-to-digital converters (ADCs) that operate

from a single power supply, VDD. The reference voltage, VREF, is

applied externally and can be set independent of the supply voltage.

The AD4002/AD4006/AD4010 power scales linearly with

throughput.

Easy Drive features reduce both signal chain complexity and

power consumption while enabling higher channel density. The

reduced input current, particularly in high-Z mode, coupled with a

long signal acquisition phase, eliminates the need for a dedicated

ADC driver. Easy Drive broadens the range of companion circuitry

that is capable of driving these ADCs (see Figure 2).

Input span compression eliminates the need to provide a

negative supply to the ADC driver amplifier while preserving

access to the full ADC code range. The input overvoltage clamp

protects the ADC inputs against overvoltage events, minimizing

disturbances on the reference pin and eliminating the need for

external protection diodes.

Fast device throughput up to 2 MSPS allows users to accurately

capture high frequency signals and to implement oversampling

techniques to alleviate the challenges associated with antialias

filter designs. Decreased serial peripheral interface (SPI) clock

rate requirements reduce digital input/output power consumption,

broadens digital host options, and simplifies the task of sending

data across digital isolation. The SPI-compatible serial user

interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by

using the separate VIO logic supply.

–25

–20

–15

–10

–5

0

5

10

15

20

25

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

INPUT DIFFERENTIAL VOLTAGE (V)

HIGH-Z DISABLED, 2MSPS

HIGH-Z ENABLED, 2MSPS

Figure 2. Input Current vs. Input Differential Voltage

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