AD4002 datasheet(34/39 Pages) AD

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AD4002/AD4006/AD4010

Data Sheet

Rev. A | Page 34 of 39

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is typically used when multiple AD4002/AD4006/

AD4010 devices are connected to an SPI-compatible digital host.

A connection diagram example using two AD4002/AD4006/

AD4010 devices is shown in Figure 59, and the corresponding

timing diagram is shown in Figure 60.

Turbo mode must be disabled to use this mode. To disable turbo

mode, set the turbo mode enable field in the configuration

A rising edge on CNV initiates a conversion and forces SDO to

high impedance. When performing conversions in this mode,

SDI must be high during the CNV rising edge. CNV must be

held high throughout the conversion and data readback phase.

When performing conversions in this mode, SDI must be high

during the CNV rising edge. Prior to the minimum conversion

time (tCONV), SDI can select other SPI devices, such as analog

multiplexers. However, SDI must be returned high before the

minimum conversion time elapses and then held high for the

maximum possible conversion time to avoid the generation of

the busy signal indicator. When the conversion is complete,

the AD4002/AD4006/AD4010 enter the acquisition phase and

power-down. There must not be any digital activity on SCK

during the conversion.

SDI is analogous to a chip select input, and each ADC result can

be read by bringing the corresponding SDI input low. Bringing

SDI low on each device outputs the MSB of the conversion

result on the corresponding SDO pin. The remaining data bits

are clocked out on SDO by subsequent SCK falling edges. The

data is valid on both SCK edges. The conversion result is clocked

out on SDO on the first 18 SCK falling edges. If the status bits are

enabled, they are shifted out on SDO on the 19th through the 24th

SCK falling edges (see the Status Bits section). SDO returns to

high impedance after the final SCK falling edge, or when SDI

goes high (whichever occurs first). If the SDO of each device is

tied together, ensure SDI is only low for one device at a time.

The user must also provide a delay of tQUIET2 between the final

SCK falling edge and the next CNV rising edge to ensure

specified performance.

SDI

SDO

CNV

SCK

DEVICE A

CONVERT

DATA IN

CLK

DIGITAL HOST

AD4002/

AD4006/

AD4010

AD4002/

AD4006/

AD4010

SDI

SDO

CNV

SCK

DEVICE B

CS1

CS2

Figure 59. CS Mode, 4-Wire Without Busy Indicator Connection Diagram

SDO

D17

D16

D15

tDIS

SCK

tHSDO

tDSDO

tEN

CONVERSION

ACQUISITION

tCONV

CYC

tACQ

ACQUISITION

SDI (CS1)

CNV

tSSDICNV

tHSDICNV

tSCK

tSCKL

tSCKH

D17

D16

SDI (CS2)

tQUIET2

Figure 60. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Diagram (Status Bits Not Shown)

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