AD4002 datasheet(25/39 Pages) AD

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Data Sheet

AD4002/AD4006/AD4010

Rev. A | Page 25 of 39

POWER SUPPLY

The AD4002/AD4006/AD4010 use two power supply pins: a core

supply (VDD) and a digital input/output interface supply (VIO).

VIO allows direct interface with any logic between 1.8 V and 5.5 V.

To reduce the number of supplies needed, VIO and VDD can be

tied together for 1.8 V operation. The ADP7118 low noise,

CMOS, low dropout (LDO) linear regulator is recommended to

power the VDD and VIO pins. The AD4002/AD4006/AD4010

are independent of power supply sequencing between VIO and

VDD. Additionally, the AD4002/AD4006/AD4010 are insensitive

to power supply variations over a wide frequency range, as

shown in Figure 32.

The AD4002/AD4006/AD4010 power down automatically at

the end of each conversion phase. Therefore, the power scales

linearly with the sampling rate. This feature makes the device

ideal for low sampling rates (even a few samples per second)

and battery-powered applications. Figure 34 shows the AD4002/

AD4006/AD4010 total power dissipation and individual power

dissipation for each rail.

DIGITAL INTERFACE

The AD4002/AD4006/AD4010 digital interface is used to

perform analog to digital conversions and to enable and disable

various features. The AD4002/AD4006/AD4010 are compatible

with SPI, QSPI™, and MICROWIRE® digital hosts and DSPs.

SCK must be set with the clock polarity (CPOL) = the clock

phase (CPHA) = 0. A 3-wire interface using the CNV, SCK, and

SDO signals minimizes wiring connections, which is useful in

applications with digital isolation. A 4-wire interface using the

SDI, CNV, SCK, and SDO signals allows CNV, which initiates

the conversions, to be independent of the readback timing (SDI).

This interface is useful in low jitter sampling or simultaneous

sampling applications. In either 3-wire or 4-wire CS mode, a

busy signal can be enabled to indicate when the conversion result

is ready. The busy signal acts as an interrupt to the digital host to

initiate data readback.

The AD4002/AD4006/AD4010 digital interface also supports

daisy-chaining multiple devices to read back results from multiple

ADCs over a single SPI bus.

Timing diagrams and explanations for each digital interface mode

are given in the CS Mode, 3-Wire Turbo Mode section through

the Daisy-Chain Mode section.

Turbo mode allows the use of slower SPI clock rates by extending

the amount of time available to clock out conversion results. Turbo

mode is enabled by setting the turbo mode enable bit to 1 in the

configuration register (see Table 12) and replaces the busy

indicator feature when enabled. The maximum throughput of

2 MSPS for the AD4002 can only be achieved with turbo mode

enabled and a minimum SCK frequency of 75 MHz (see Serial

Clock Frequency Requirements section). See the CS Mode, 3-

Wire Turbo Mode section and CS Mode, 4-Wire Turbo Mode for

descriptions of turbo mode operation.

Status bits can also be clocked out at the end of the conversion data

if the status bits are enabled in the configuration register (the Status

Bits section).

For isolated systems, the ADuM141D is recommended to support

the 75 MHz SCK frequency required to run the AD4002 at the full

throughput of 2 MSPS.

The state of SDO on power-up is either low or high-Z, depending

on the states of CNV and SDI, as shown in Table 11.

Table 11. State of SDO on Power-Up

CNV

SDI

SDO

Low

High-Z

Configuration Register Details

The AD4002/AD4006/AD4010 features are controlled via the

configuration register. The configuration register is eight bits

wide and contains enable bits for the status bits, span compression,

high-Z mode, and turbo mode, as well as an overvoltage detection

flag. The 16-bit SPI instructions are used to read from and write

to the contents in the configuration register. Table 12 shows the

locations and descriptions of each field in the configuration

Serial Clock Frequency Requirements

The AD4002/AD4006/AD4010 digital interface minimizes the

SCK frequency required for reading back conversion results, even

when operating at high throughput. The minimum SCK frequency

required for a given application depends on the number of bits

being read on SDO, whether turbo mode is enabled or disabled,

and the throughput in use.

See Table 13 for several examples of SCK frequency requirements

for different throughputs.

Note that the SCK frequency must obey the minimum SCK

period specification for the given VIO level and interface mode

(see tSCK in Table 2).

The minimum SCK frequency (fSCK) required to access the

conversion result plus status bits when turbo mode is enabled is

calculated with the following equation:

SCK

CYC

QUIET









where:

ND is the ADC resolution (18 bits).

NS is the number of status bits being accessed.

tCYC, tQUIET1, tEN and tQUIET2 correspond to timing specifications

described in Table 2

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